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公开(公告)号:US10164122B2
公开(公告)日:2018-12-25
申请号:US15884729
申请日:2018-01-31
发明人: Shih-Yen Lin , Chi-Wen Liu , Chong-Rong Wu , Xiang-Rui Chang
IPC分类号: H01L21/02 , H01L29/786 , H01L29/66 , H01L29/24 , H01L29/778 , H01L29/267 , H01L29/417 , H01L29/16
摘要: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
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公开(公告)号:US09711607B1
公开(公告)日:2017-07-18
申请号:US15130527
申请日:2016-04-15
发明人: Che-Wei Yang , Chi-Wen Liu , Hao-Hsiung Lin , Ling-Yen Yeh
CPC分类号: H01L29/42392 , H01L21/02444 , H01L21/02532 , H01L21/02546 , H01L21/02603 , H01L21/02636 , H01L21/02645 , H01L21/2018 , H01L27/1281 , H01L29/0673 , H01L29/66469 , H01L29/66477 , H01L29/775 , H01L29/78
摘要: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
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公开(公告)号:US20190207035A1
公开(公告)日:2019-07-04
申请号:US16353290
申请日:2019-03-14
发明人: Miin-Jang Chen , Chi-Wen Liu , Bo-Ting Lin
IPC分类号: H01L29/78 , H01L27/1159 , H01L27/11521 , H01L21/28 , H01L29/66 , H01L29/51 , H01L21/02 , H01L49/02
CPC分类号: H01L29/78391 , H01L21/02189 , H01L21/02274 , H01L21/0228 , H01L21/28291 , H01L27/11521 , H01L27/1159 , H01L28/60 , H01L29/516 , H01L29/6684
摘要: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.
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公开(公告)号:US20190088757A1
公开(公告)日:2019-03-21
申请号:US16195591
申请日:2018-11-19
发明人: Che-Wei Yang , Chi-Wen Liu , Hao-Hsiung Lin , Ling-Yen Yeh
IPC分类号: H01L29/423 , H01L21/02 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/06 , H01L21/20 , H01L27/12
摘要: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
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公开(公告)号:US10141412B2
公开(公告)日:2018-11-27
申请号:US15333442
申请日:2016-10-25
发明人: Yuh-Renn Wu , Chi-Wen Liu , Shou-Fang Chen
IPC分类号: H01L29/06 , H01L29/772 , H01L29/24 , H01L29/04 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/786
摘要: A field effect transistor (FET) includes a gate dielectric layer, a two-dimensional (2D) channel layer formed on the gate dielectric layer and a gate electrode. The 2D channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET. The 2D channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region. A source electrode covers the first finger regions, and a drain electrode covers the second finger regions.
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6.
公开(公告)号:US10068995B2
公开(公告)日:2018-09-04
申请号:US15210388
申请日:2016-07-14
发明人: Fang-Liang Lu , CheeWee Liu , Chi-Wen Liu , Shih-Hsien Huang , I-Hsieh Wong
IPC分类号: H01L29/76 , H01L29/66 , H01L21/268 , H01L21/324 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/167 , H01L29/78
摘要: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.
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公开(公告)号:US09577049B1
公开(公告)日:2017-02-21
申请号:US14989259
申请日:2016-01-06
发明人: Shih-Yen Lin , Chong-Rong Wu , Chi-Wen Liu
IPC分类号: H01L29/24 , H01L29/45 , H01L29/417 , H01L29/78 , H01L29/66 , H01L21/443
CPC分类号: H01L21/443 , H01L29/41733 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/78 , H01L29/78618 , H01L29/78681
摘要: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a semiconductor layer over the substrate. The semiconductor layer includes a transition metal chalcogenide. The semiconductor device structure includes a source electrode and a drain electrode over and connected to the semiconductor layer and spaced apart from each other by a gap. The source electrode and the drain electrode are made of graphene.
摘要翻译: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的半导体层。 半导体层包括过渡金属硫族化物。 半导体器件结构包括在半导体层之上并连接到半导体层并且通过间隙彼此间隔开的源电极和漏电极。 源电极和漏电极由石墨烯制成。
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公开(公告)号:US10147603B2
公开(公告)日:2018-12-04
申请号:US15197004
申请日:2016-06-29
发明人: Shih-Yen Lin , Chi-Wen Liu , Si-Chen Lee , Chong-Rong Wu , Kuan-Chao Chen
IPC分类号: H01L21/336 , H01L21/02 , H01L21/324 , H01L29/66
摘要: In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS2 layer. Source and drain electrodes are formed on the MoS2 layer. The MoS2 layer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoS2 layer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.
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公开(公告)号:US10854724B2
公开(公告)日:2020-12-01
申请号:US16195591
申请日:2018-11-19
发明人: Che-Wei Yang , Chi-Wen Liu , Hao-Hsiung Lin , Ling-Yen Yeh
IPC分类号: H01L29/423 , H01L29/06 , H01L29/66 , H01L29/775 , H01L21/02 , H01L29/78 , H01L27/12 , H01L21/20
摘要: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
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公开(公告)号:US10340383B2
公开(公告)日:2019-07-02
申请号:US15277079
申请日:2016-09-27
发明人: Huang-Siang Lan , CheeWee Liu , Chi-Wen Liu , Shih-Hsien Huang , I-Hsieh Wong , Hung-Yu Yeh , Chung-En Tsai
IPC分类号: H01L29/78 , H01L29/08 , H01L29/10 , H01L29/165 , H01L27/092 , H01L21/02 , H01L21/8238 , H01L29/66
摘要: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm−3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
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