公开(公告)号：US07971014B2

公开(公告)日：2011-06-28

申请号：US12198473

申请日：2008-08-26

申请人： Kenichiro Yoshii ,  Hiroshi Yao ,  Tomohide Jokan ,  Tatsunori Kanai

发明人： Kenichiro Yoshii ,  Hiroshi Yao ,  Tomohide Jokan ,  Tatsunori Kanai

IPC分类号： G06F12/16 ,  G06F13/00

CPC分类号： G06F11/1441 ,  G06F11/141

摘要： In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.

摘要翻译： 在信息处理装置中，当发出写入非易失性的主存储单元的存储内容的指令时，从备份中提取包含在具有读取许可的设置的备份数据中的数据和写入目的地地址 存储在非易失性的备份存储单元中的数据。 此外，根据从备份数据提取的数据和写入目的地地址，将数据写入由写入目的地址指示的主存储单元的存储区域。

公开(公告)号：US07761779B2

公开(公告)日：2010-07-20

申请号：US11519797

申请日：2006-09-13

申请人： Tatsunori Kanai ,  Kenichiro Yoshii

发明人： Tatsunori Kanai ,  Kenichiro Yoshii

IPC分类号： G06F12/14

CPC分类号： G06F11/1032

摘要： An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.

摘要翻译： 访问控制装置包括奇偶校验生成器，其生成要写入存储器的原始数据的奇偶校验; 以及奇偶校验加法器，通过将奇偶校验与原始数据相加来生成奇偶校验相加数据; 第一校正子发生器，其产生第一掩模数据的第一校正子，以掩蔽所述奇偶校验相加数据。 第一个综合征是与写入器访问存储器时要使用的第一访问代码预先相关联的值。 该装置还包括：第一掩模发生器，其基于第一综合征，第一访问码和第一存储器地址生成第一掩模数据; 第一XOR单元，通过计算奇偶校验相加数据和第一掩码数据之间的异或来获得第一后操作数据; 以及将第一操作后数据写入存储器的写入单元。

公开(公告)号：US07653861B2

公开(公告)日：2010-01-26

申请号：US11523003

申请日：2006-09-19

申请人： Tatsunori Kanai ,  Kenichiro Yoshii

发明人： Tatsunori Kanai ,  Kenichiro Yoshii

IPC分类号： H03M13/00

CPC分类号： G06F12/1466 ,  G06F11/1016 ,  G06F12/1408 ,  G06F21/79

摘要： An access control apparatus includes a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer that requests writing of the write data in the memory accesses the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; and a write address converter that converts the write address into another address determined by the writer access ID.

摘要翻译： 一种访问控制装置，包括：写入器校验发生器，其生成写入器掩码数据的写入器校验器以掩蔽奇偶校验相加数据;写入器校验器与写入器访问ID相关联，当写入器请求写入数据到存储器中时 访问内存 写入掩码生成器，其基于写入器综合符，写入器访问ID和写入器写入写入数据的存储器中的写入地址生成写入器掩模数据; 第一XOR计算器，通过计算奇偶校验相加数据和写入器掩码数据之间的异或来获得第一后操作数据; 以及将写入地址转换成由写入器访问ID确定的另一地址的写入地址转换器。

公开(公告)号：US20070136647A1

公开(公告)日：2007-06-14

申请号：US11519797

申请日：2006-09-13

申请人： Tatsunori Kanai ,  Kenichiro Yoshii

发明人： Tatsunori Kanai ,  Kenichiro Yoshii

IPC分类号： H03M13/00

CPC分类号： G06F11/1032

摘要： An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.

摘要翻译： 访问控制装置包括奇偶校验生成器，其生成要写入存储器的原始数据的奇偶校验; 以及奇偶校验加法器，通过将奇偶校验与原始数据相加来生成奇偶校验相加数据; 第一校正子发生器，其产生第一掩模数据的第一校正子，以掩蔽所述奇偶校验相加数据。 第一个综合征是与写入器访问存储器时要使用的第一访问代码预先相关联的值。 该装置还包括：第一掩模发生器，其基于第一综合征，第一访问码和第一存储器地址生成第一掩模数据; 第一XOR单元，通过计算奇偶校验相加数据和第一掩码数据之间的异或来获得第一后操作数据; 以及将第一操作后数据写入存储器的写入单元。

公开(公告)号：US07054912B2

公开(公告)日：2006-05-30

申请号：US10092540

申请日：2002-03-08

申请人： Tatsunori Kanai ,  Toshibumi Seki ,  Kenichiro Yoshii ,  Hideaki Sato ,  Takayuki Miyazawa ,  Haruhiko Toyama ,  Yasuhiro Kimura ,  Hideki Yoshida

发明人： Tatsunori Kanai ,  Toshibumi Seki ,  Kenichiro Yoshii ,  Hideaki Sato ,  Takayuki Miyazawa ,  Haruhiko Toyama ,  Yasuhiro Kimura ,  Hideki Yoshida

IPC分类号： G06F15/167

CPC分类号： H04L67/2828 ,  H04L29/06 ,  H04L67/2876 ,  H04L69/04 ,  H04L69/329

摘要： In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices.

公开(公告)号：US08397017B2

公开(公告)日：2013-03-12

申请号：US12723846

申请日：2010-03-15

申请人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F13/00

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7207

摘要： A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.

摘要翻译： 易失性管理存储器存储用于管理存储介质的使用状态的管理信息。 管理信息存储单元将管理信息分成多个分割片，并将它们分别存储在存储介质中。 主控制器在存储分割片的同时从主机装置接收命令，根据存储各分割片之间的命令对存储介质执行数据处理，根据数据更新分割成分割片的管理信息 处理内容，并创建表示管理信息的更新内容的日志。 日志存储单元将日志存储在存储介质中。 恢复单元将存储在存储介质中的分割信息作为管理信息读取到管理存储器，根据存储在存储介质中的日志更新管理信息，并恢复更新的管理信息。

公开(公告)号：US20110214033A1

公开(公告)日：2011-09-01

申请号：US12885962

申请日：2010-09-20

申请人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F11/08 ,  G06F12/00

CPC分类号： G06F11/1048

摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other. The identification information associates the second data and the redundant information, and the region specifying information specifies the storage regions in the semiconductor memory chips to which the first data included in the second data and the redundant information are written.

摘要翻译： 根据一个实施例，半导体存储器件包括具有可写入存储区域的数据被写入的半导体存储器芯片。 数据具有一个或多个第一数据，并且一个或多个第一数据包括第二数据。 该装置包括：确定单元，其确定写入第一数据的半导体存储器芯片的规定数量以下; 写入控制器，其将从第二数据计算出的第一数据和冗余信息写入第二数据中的错误，并将其写入到所确定的半导体存储器芯片中的可写入存储区域中; 以及存储单元，其存储彼此相关联的识别信息和区域指定信息。 所述识别信息将所述第二数据和所述冗余信息相关联，并且所述区域指定信息指定在所述第二数据中包含的所述第一数据和所述冗余信息被写入的所述半导体存储器芯片中的存储区域。

公开(公告)号：US07334023B2

公开(公告)日：2008-02-19

申请号：US10396521

申请日：2003-03-26

申请人： Yuichi Koba ,  Yasuhiro Kimura ,  Kenichiro Yoshii ,  Atsushi Shono ,  Hideaki Sato ,  Toshibumi Seki

发明人： Yuichi Koba ,  Yasuhiro Kimura ,  Kenichiro Yoshii ,  Atsushi Shono ,  Hideaki Sato ,  Toshibumi Seki

IPC分类号： G06F15/167 ,  G06F15/16

CPC分类号： H04L29/06 ,  H04L67/02 ,  H04L67/2823 ,  H04L67/2852 ,  H04L67/2895 ,  H04L67/34 ,  H04L69/04 ,  H04L69/329

摘要： In a client server system, the network load is reduced by using the fingerprint compression and the differential compression, by providing the proxy server at the server side and using the general purpose browser at the client side, without requiring a separate proxy server at the client side. The client downloads and installs a fingerprint cache processing engine as a plug-in.

摘要翻译： 在客户服务器系统中，通过在服务器端提供代理服务器，并在客户端使用通用浏览器，通过使用指纹压缩和差分压缩来减少网络负载，而不需要客户端上的单独的代理服务器 侧。 客户端下载并安装指纹缓存处理引擎作为插件。

公开(公告)号：US08453033B2

公开(公告)日：2013-05-28

申请号：US12885962

申请日：2010-09-20

申请人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： H03M13/09

CPC分类号： G06F11/1048

摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other. The identification information associates the second data and the redundant information, and the region specifying information specifies the storage regions in the semiconductor memory chips to which the first data included in the second data and the redundant information are written.

摘要翻译： 根据一个实施例，半导体存储器件包括具有可写入存储区域的数据被写入的半导体存储器芯片。 数据具有一个或多个第一数据，并且一个或多个第一数据包括第二数据。 该装置包括：确定单元，其确定写入第一数据的半导体存储器芯片的规定数量以下; 写入控制器，其将从第二数据计算出的第一数据和冗余信息写入第二数据中的错误，并将其写入到所确定的半导体存储器芯片中的可写入存储区域中; 以及存储单元，其存储彼此相关联的识别信息和区域指定信息。 所述识别信息将所述第二数据和所述冗余信息相关联，并且所述区域指定信息指定在所述第二数据中包含的所述第一数据和所述冗余信息被写入的所述半导体存储器芯片中的存储区域。

公开(公告)号：US08392476B2

公开(公告)日：2013-03-05

申请号：US12885941

申请日：2010-09-20

申请人： Shigehiro Asano ,  Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno

发明人： Shigehiro Asano ,  Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno

IPC分类号： G06F17/30

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.

摘要翻译： 根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩 以日志结构的方式。 半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。