公开(公告)号：US06897505B2

公开(公告)日：2005-05-24

申请号：US10612233

申请日：2003-07-02

申请人： Thomas J. Aton

发明人： Thomas J. Aton

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/08 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/0805

摘要： An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.

摘要翻译： 片上模拟电容器。 金属互连结构用于形成电容器，并且互连结构内相同极性的交叉指状物通过金属通孔彼此上下连接以形成金属壁，其通过利用通孔侧壁电容来增加总电容 。

公开(公告)号：US06787469B2

公开(公告)日：2004-09-07

申请号：US10227615

申请日：2002-08-23

申请人： Theodore W. Houston ,  Robert A. Soper ,  Thomas J. Aton

发明人： Theodore W. Houston ,  Robert A. Soper ,  Thomas J. Aton

IPC分类号： H01L21302

CPC分类号： H01L21/32139 ,  H01L27/1104

摘要： A system for fabricating a mixed voltage integrated circuit is disclosed in which a gate is provided that contains a gate oxide and a gate conductor on a substrate. A first mask is deposited to pattern the length of the gate by etching, and a second mask pattern is deposited and used to etch the width of the gate, with or without a hard mask.

摘要翻译： 公开了一种用于制造混合电压集成电路的系统，其中提供了在基板上包含栅极氧化物和栅极导体的栅极。 沉积第一掩模以通过蚀刻来对栅极的长度进行图案化，并且沉积第二掩模图案并且使用第二掩模图案来蚀刻具有或不具有硬掩模的栅极的宽度。

公开(公告)号：US06635916B2

公开(公告)日：2003-10-21

申请号：US09935519

申请日：2001-08-23

申请人： Thomas J. Aton

发明人： Thomas J. Aton

IPC分类号： H01L27108

CPC分类号： H01L27/0805

摘要： An on-chip analog capacitor. Metal interconnect structures are used to form the capacitor, and the interdigitated fingers of like polarity within the interconnect structure are connected above and below to one another by metal vias to form a wall of metal which increases total capacitance by taking advantage of the via sidewall capacitance.

公开(公告)号：US5294801A

公开(公告)日：1994-03-15

申请号：US928258

申请日：1992-08-11

申请人： Thomas J. Aton ,  Denis F. Spicer

发明人： Thomas J. Aton ,  Denis F. Spicer

IPC分类号： H01L21/027 ,  G03F7/20 ,  H01J37/22

CPC分类号： G03F7/2037 ,  Y10S430/143

摘要： An electron beam imaging system (10) includes a photoemitter plate (12). An optical image beam (15) is directed through a pattern mask (18), which is imaged onto the photoemitter (12). The photoemitter (12) emits electrons from those unmasked regions illuminated by the optical image beam, emitting an extended-source electron beam that carries the mask image. The extended-source electron beam is focused (34) onto a device under fabrication (40), providing a single-stage electron lithographic patterning function. The optical source (16) is chosen so that optical image beam energy is nearly identical to the work function for the photoemissive coating (14) of the photoemitter (12). As a result, the photoemitter (12) emits electrons with substantially zero kinetic energy, allowing the emitted electrons to be accelerated through the electron beam focusing elements (34) with very nearly identical electron velocities, thereby minimizing chromatic aberrations. In one embodiment, an aperture (85) is used to limit the extended-source electron beam to those electrons with trajectories requiring no more than a maximum amount of focusing, thereby minimizing spherical aberrations.

摘要翻译： 电子束成像系统（10）包括发光板（12）。 光学图像束（15）被引导通过图案掩模（18），其被成像到光发射器（12）上。 光发射器（12）从由光学图像束照射的那些未屏蔽区域发射电子，发射携带掩模图像的扩展源电子束。 扩展源电子束被聚焦（34）到制造设备（40）上，提供单级电子光刻图案功能。 选择光源（16）使得光学图像束能量几乎等于光发射器（12）的光发射涂层（14）的功函数。 结果，光发射器（12）以基本上为零的动能发射电子，允许发射的电子以非常接近相同的电子速度加速穿过电子束聚焦元件（34），从而最小化色差。 在一个实施例中，使用孔径（85）将扩展源电子束限制到具有不超过最大聚焦量的轨迹的那些电子，从而使球面像差最小化。

公开(公告)号：US5156942A

公开(公告)日：1992-10-20

申请号：US378116

申请日：1989-07-11

申请人： Thomas J. Aton ,  Denis F. Spicer

发明人： Thomas J. Aton ,  Denis F. Spicer

IPC分类号： H01L21/027 ,  G03F7/20

CPC分类号： G03F7/2037 ,  Y10S430/143

摘要： An electron beam imaging system (10) includes a photoemitter plate (12). An optical image beam (15) is directed through a pattern mask (18), which is imaged onto the photoemitter (12). The photoemitter (12) emits electrons from those unmasked regions illuminated by the optical image beam, emitting an extended-source electron beam that carries the mask image. The extended-source electron beam is focused (34) onto a device under fabrication (40), providing a single-stage electron lithographic patterning function. The optical source (16) is chosen so that the optical image beam energy is nearly identical to the work function for the photoemissive coating (14) of the photoemitter (12). As a result, the photoemitter (12) emits electrons with substantially zero kinetic energy, allowing the emitted electrons to be accelerated through the electron beam focusing elements (34) with very nearly identical electron velocities, thereby minimizing chromatic aberrations. In one embodiment, an aperture (85) is used to limit the extended-source electron beam to those electrons with trajectories requiring no more than a maximum amount of focusing, thereby minimizing spherical aberrations.

摘要翻译： 电子束成像系统（10）包括发光板（12）。 光学图像束（15）被引导通过图案掩模（18），其被成像到光发射器（12）上。 光发射器（12）从由光学图像束照射的那些未屏蔽区域发射电子，发射携带掩模图像的扩展源电子束。 扩展源电子束被聚焦（34）到制造设备（40）上，提供单级电子光刻图案功能。 选择光源（16）使得光学图像束能量几乎与光发射器（12）的光发射涂层（14）的功函数相同。 结果，光发射器（12）以基本上为零的动能发射电子，允许发射的电子以非常接近相同的电子速度加速穿过电子束聚焦元件（34），从而最小化色差。 在一个实施例中，使用孔径（85）将扩展源电子束限制到具有不超过最大聚焦量的轨迹的那些电子，从而使球面像差最小化。

公开(公告)号：US10199380B2

公开(公告)日：2019-02-05

申请号：US13043163

申请日：2011-03-08

申请人： Theodore W. Houston ,  Thomas J. Aton ,  Scott W. Jessen

发明人： Theodore W. Houston ,  Thomas J. Aton ,  Scott W. Jessen

IPC分类号： H01L27/11 ,  H01L27/02

摘要： An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

公开(公告)号：US08580685B2

公开(公告)日：2013-11-12

申请号：US13447629

申请日：2012-04-16

申请人： Thomas J. Aton ,  Donald Plumton

发明人： Thomas J. Aton ,  Donald Plumton

IPC分类号： H01L21/00

CPC分类号： H01L21/31144 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.

摘要翻译： 一种用于制造集成电路的方法包括以下步骤：提供具有半导体表面的衬底; 在半导体表面上提供硬掩模材料。 对于集成电路的至少一个掩蔽级别：提供分割为第一掩模和至少一个第二掩模的掩蔽级别的掩模图案，所述第一掩模提供第一栅格图案中的特征，并且所述至少一个第二掩模提供特征 在第二格栅图案中，其中第一和第二格栅图案具有在至少一个区域上彼此交错的各自特征; 用第一掩模施加第一光致抗蚀剂层; 使用第一掩模曝光第一格栅图案; 显影第一光致抗蚀剂层; 蚀刻硬掩模材料以将衬底的表面中的第一栅格图案转移; 去除第一光致抗蚀剂层。

公开(公告)号：US08455180B2

公开(公告)日：2013-06-04

申请号：US12915974

申请日：2010-10-29

申请人： James Walter Blatchford ,  Yong Seok Choi ,  Thomas J. Aton

发明人： James Walter Blatchford ,  Yong Seok Choi ,  Thomas J. Aton

IPC分类号： G03F7/20

CPC分类号： G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

摘要： A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8W1 to 1.3W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

摘要翻译： 形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。 相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。 相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。 相邻虚拟特征和最近的门级特征之间的间隔（i）维持栅极间距，或（ii）提供> = 2倍栅极间距的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。

公开(公告)号：US20120258593A1

公开(公告)日：2012-10-11

申请号：US13530410

申请日：2012-06-22

申请人： Theodore W. Houston ,  Thomas J. Aton ,  Scott W. Jessen

发明人： Theodore W. Houston ,  Thomas J. Aton ,  Scott W. Jessen

IPC分类号： H01L21/768

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11 ,  Y10S257/903

摘要： An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

公开(公告)号：US20120107729A1

公开(公告)日：2012-05-03

申请号：US12915974

申请日：2010-10-29

申请人： James Walter Blatchford ,  Yong Seok Choi ,  Thomas J. Aton

发明人： James Walter Blatchford ,  Yong Seok Choi ,  Thomas J. Aton

IPC分类号： G03F1/00 ,  H01L21/336 ,  G06F17/50

CPC分类号： G03F7/20 ,  G03F1/36 ,  G03F1/38 ,  G06F17/50 ,  G06F17/5068 ,  H01L21/28123

摘要： A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8W1 to 1.3W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ≧2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

摘要翻译： 形成包括MOS晶体管的IC的方法包括使用栅极掩模形成在有源区上具有线宽度W1的第一有源栅极特征和具有线宽0.8W1至1.3W1的相邻虚拟特征。 相邻的虚拟特征具有与第一有效栅极特征相邻的第一侧和与第一侧相对的第二侧上的最近的栅极级特征。 相邻的虚拟特征基于到第一有源栅极特征的距离来限定栅极间距，或者相邻的虚设特征维持包括第一有源栅极特征的栅极阵列中的栅极间距。 相邻的虚拟特征与最近的栅极电平特征（i）之间的间隔保持栅极间距，或（ii）提供比栅极间距大2倍的SRAF使能距离，并且栅极掩模包括在SRAF距离上的SRAF。