公开(公告)号：US07313777B1

公开(公告)日：2007-12-25

申请号：US11194357

申请日：2005-08-01

申请人： Jie Yang ,  Luigi Capodieci

发明人： Jie Yang ,  Luigi Capodieci

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Methods and apparatus for checking layouts of circuit features are provided. In one aspect, a method of designing a layout for a circuit feature is provided that includes deriving a function which relates a size and a plurality of aerial image parameters of the circuit feature to a probability of a printing fault in using a lithographic process to pattern the circuit feature. A layout for the circuit feature is created. The function is used to determine a probability of a printing fault in using the lithographic process to pattern the circuit feature and adjust the layout of the circuit feature as necessary in view of the determined probability of printing fault.

摘要翻译： 提供了检查电路特性布局的方法和装置。 在一个方面，提供了一种设计用于电路特征的布局的方法，其包括导出将电路特征的尺寸和多个空间图像参数与使用光刻处理模式的打印故障的概率相关联的功能 电路功能。 创建电路功能的布局。 考虑到确定的打印故障概率，该功能用于确定在使用光刻工艺绘制电路特征并根据需要调整电路特征的布局来确定打印故障的概率。

公开(公告)号：US06978438B1

公开(公告)日：2005-12-20

申请号：US10677154

申请日：2003-10-01

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G03F1/14 ,  G06F17/50

CPC分类号： G03F1/36

摘要： A method and associated computer program for making optical proximity corrections for a reticle layout topology. Edge segments of the reticle layout topology are manipulated to generate a corrected reticle layout accounting for optical distortions and, based on the corrected reticle layout, a plurality of individual figure of merit values are generated. A generalized figure of merit (GFOM) using the plurality of individual figure of merit values is then generated.

摘要翻译： 一种用于对光罩布局拓扑进行光学邻近校正的方法和相关联的计算机程序。 处理标线布局拓扑的边缘片段以产生校正的光掩模布局，以计算光学失真，并且基于校正的标线布局，生成多个单独的品质因数值。 然后生成使用多个个体品质因数值的广义品质因数（GFOM）。

公开(公告)号：US20050243299A1

公开(公告)日：2005-11-03

申请号：US10833651

申请日：2004-04-28

申请人： Christopher Spence ,  Todd Lukanc ,  Luigi Capodieci ,  Joerg Reiss ,  Sarah McGowan

发明人： Christopher Spence ,  Todd Lukanc ,  Luigi Capodieci ,  Joerg Reiss ,  Sarah McGowan

IPC分类号： G03F7/20 ,  G03B27/72

CPC分类号： G03F7/7085 ,  G03F7/70133 ,  G03F7/70441 ,  G03F7/70666 ,  G03F7/70941

摘要： A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.

摘要翻译： 一种用于产生形成投影光刻系统的一部分的照明器的照明强度分布的系统和方法。 来自照明器的辐射被投射到具有多个孔的照明轮廓掩模，使得每个孔通过辐射的不同部分。 检测并组装每个不同部分的辐射的强度以形成照射强度分布。

公开(公告)号：US06458606B2

公开(公告)日：2002-10-01

申请号：US09854272

申请日：2001-05-11

申请人： Marina V. Plat ,  Luigi Capodieci ,  Scott A. Bell ,  Todd Lukanc

发明人： Marina V. Plat ,  Luigi Capodieci ,  Scott A. Bell ,  Todd Lukanc

IPC分类号： G01R3126

CPC分类号： H01L22/34

摘要： Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.

摘要翻译： 用于生产半导体晶片的测试晶片包括形成测试晶片的操作电路的多个有源结构。 活性结构密集地存在于测试晶片的某些区域，并且稀疏地填充在测试晶片的其它区域中。 已经观察到，相同结构的临界尺寸，例如蚀刻偏压和斜率分布根据结构是否形成在密集或人烟稀少的区域中而变化。 在测试晶片上形成虚拟结构，以便在测试晶片上均匀分布结构的密度。

公开(公告)号：US06272392B1

公开(公告)日：2001-08-07

申请号：US09205898

申请日：1998-12-04

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G06F1900

CPC分类号： G03F7/705 ,  G03F7/706 ,  H01J37/304 ,  H01J2237/30433 ,  H01J2237/30455 ,  H01J2237/317

摘要： A method (250) of extracting effective imaging system aberrations from test data collected from test structures (220) constructed from a lithography system having an imaging system associated therewith includes inputting (264) experimental critical dimension data corresponding to fabricated features (220) on a substrate (212) to a neural network (208). The method (250) also includes inputting (266) nominal critical dimension data corresponding to the fabricated features on the substrate (212) to the neural network (208) and determining (268) the effective aberrations of the imaging system associated with the lithography system used to fabricate the features (220) using the neural network (208).

摘要翻译： 从由具有与其相关联的成像系统的光刻系统构成的测试结构（220）收集的测试数据中提取有效的成像系统像差的方法（250）包括：输入（264）对应于制造特征（220）的实验临界尺寸数据 衬底（212）到神经网络（208）。 方法（250）还包括将对应于衬底（212）上的制造特征的标称临界尺寸数据输入（266）到神经网络（208），并且确定（268）与光刻系统相关联的成像系统的有效像差 用于使用神经网络（208）制造特征（220）。

公开(公告)号：US08555215B2

公开(公告)日：2013-10-08

申请号：US13400445

申请日：2012-02-20

申请人： Yi Zou ,  Swamy Maddu ,  Lynn T. Wang ,  Vito Dai ,  Luigi Capodieci ,  Peng Xie

发明人： Yi Zou ,  Swamy Maddu ,  Lynn T. Wang ,  Vito Dai ,  Luigi Capodieci ,  Peng Xie

IPC分类号： G06F17/50

CPC分类号： G03F1/70

摘要： Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

摘要翻译： 提供制造半导体器件的方法。 在一个实施例中，制造半导体器件的方法包括扫描电路设计布局并提出用于分解布局的图案。 然后将所提出的模式与包括禁止模式类别和优选模式类别的先前模式的库进行比较。 如果所选择的提议模式匹配禁止模式，则删除所选择的提议模式。 如果所选择的提出的模式匹配优选模式，则所选择的提出的模式被识别用于分解的布局。 分辨的布局是从识别的图案生成的。 基于分解的布局制造多个掩模。 然后用半导体衬底上的多个掩模进行多重图形化光刻技术。

公开(公告)号：US06583041B1

公开(公告)日：2003-06-24

申请号：US09562502

申请日：2000-05-01

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： H01L214763

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate layer over the first portion of the microdevice component; forming a second regular array of lines and spaces from a second layer of material deposited on the intermediate layer; patterning the second regular array of lines and spaces to form a second portion of the microdevice component; and forming contact holes in the intermediate layer to establish conductivity between the first portion of the microdevice component and the second portion of the microdevice component.

摘要翻译： 一种制造微型器件的方法，具有以下步骤：从沉积在衬底上的第一材料层形成线和间隔的第一规则阵列; 图案化第一规则阵列的线和空格以形成微装置部件的第一部分; 在所述微器件部件的第一部分上提供中间层; 从沉积在中间层上的第二材料层形成线和空间的第二规则阵列; 图案化第二规则阵列的线和间隔以形成微器件部件的第二部分; 以及在中间层中形成接触孔，以在微器件部件的第一部分和微器件部件的第二部分之间建立导电性。

公开(公告)号：US06553562B2

公开(公告)日：2003-04-22

申请号：US09985621

申请日：2001-11-05

申请人： Luigi Capodieci ,  Juan Andres Torres Robles ,  Lodewijk Hubertus Van Os

发明人： Luigi Capodieci ,  Juan Andres Torres Robles ,  Lodewijk Hubertus Van Os

IPC分类号： G06F1750

CPC分类号： G03F1/70 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70466

摘要： A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying “horizontal” critical features and “vertical” critical features from a plurality of features forming a layout; identifying interconnection areas which are areas in which one of the horizontal critical features or the vertical critical features contacts another feature of the layout; defining a set of primary parameters on the basis of the proximity of the plurality of features relative to one another; and generating an edge modification plan for each interconnection area based on the primary parameters. A horizontal mask pattern is then generated by compiling the horizontal critical features, a first shield plan for the vertical critical features and the interconnection areas containing a horizontal critical feature modified by the edge modification plan. A vertical mask pattern is then generated by compiling the vertical critical features, a second shield plan for the horizontal critical features and the interconnection areas containing a vertical critical feature modified by the edge modification plan.

公开(公告)号：US06262435B1

公开(公告)日：2001-07-17

申请号：US09203616

申请日：1998-12-01

申请人： Marina V. Plat ,  Luigi Capodieci ,  Scott A. Bell ,  Todd Lukanc

发明人： Marina V. Plat ,  Luigi Capodieci ,  Scott A. Bell ,  Todd Lukanc

IPC分类号： H01L2358

CPC分类号： H01L22/34

摘要： Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.

摘要翻译： 用于生产半导体晶片的测试晶片包括形成测试晶片的操作电路的多个有源结构。 活性结构密集地存在于测试晶片的某些区域，并且稀疏地填充在测试晶片的其它区域中。 已经观察到，相同结构的临界尺寸，例如蚀刻偏压和斜率分布根据结构是否形成在密集或人烟稀少的区域中而变化。 在测试晶片上形成虚拟结构，以便在测试晶片上均匀分布结构的密度。

公开(公告)号：US6044007A

公开(公告)日：2000-03-28

申请号：US275165

申请日：1999-03-24

申请人： Luigi Capodieci

发明人： Luigi Capodieci

IPC分类号： G03F1/00 ,  G03F7/20 ,  G11C13/00

CPC分类号： G03F7/70425 ,  G03F1/36

摘要： A data storage medium contains mask layout data for use in writing a mask includes a first mask data portion which corresponds to a feature having an interior corner. The first mask data portion corresponding to the interior corner includes a multi-level or stepped inner serif in the interior corner which provides for improved writeability of OPC independent of process push or bias. Alternatively, the data storage medium contains mask layout data which includes a second mask data portion. The second mask data portion corresponds to a feature having an exterior corner and includes a multi-level or stepped outer serif on the exterior corner. The stepped outer serif also provides for improved writeability of OPC independent of process push or bias.

摘要翻译： 数据存储介质包含用于写入掩模的掩模布局数据，其包括对应于具有内角的特征的第一掩模数据部分。 对应于内角的第一掩模数据部分包括在内角中的多级或阶梯式内衬里，其提供独立于过程推动或偏压的OPC的改进的可写性。 或者，数据存储介质包含包括第二掩码数据部分的掩模布局数据。 第二掩模数据部分对应于具有外角的特征，并且在外角上包括多级或阶梯式外衬里。 阶梯式外衬片还提供独立于过程推动或偏压的OPC的可写性。