公开(公告)号：US08537520B2

公开(公告)日：2013-09-17

申请号：US13237619

申请日：2011-09-20

申请人： Shinji Miyano

发明人： Shinji Miyano

IPC分类号： H01G4/02 ,  H02N1/00

CPC分类号： H02N1/006

摘要： A semiconductor device applies a hold voltage Vhold to an upper electrode of an electrostatic actuator and a ground voltage to a lower electrode. After the semiconductor device sets the voltage of the lower electrode to a test voltage Vtest, it eliminates the hold voltage Vhold from the upper electrode and places the voltage of the upper electrode in a high impedance state. The potential difference between the upper electrode and the lower electrode is set to Vhold−Vtest=Vmon. Thereafter, the voltage of the lower electrode is returned to the ground voltage. Whether the electrostatic actuator is placed in an open state or in a closed state is determined by measuring the capacitance between the electrodes based on the amount of drop of the voltage of the upper electrode due to capacitance coupling at the time.

摘要翻译： 半导体器件向静电致动器的上电极施加保持电压Vhold，将接地电压施加到下电极。 在半导体器件将下电极的电压设定为测试电压Vtest之后，消除了来自上电极的保持电压Vhold，并将上电极的电压置于高阻抗状态。 上电极和下电极之间的电位差被设定为Vhold-Vtest = Vmon。 此后，下电极的电压返回接地电压。 静电致动器处于打开状态或处于闭合状态是通过基于由于电容耦合引起的上部电极的电压的下降量来测量电极之间的电容来确定的。

公开(公告)号：US08310884B2

公开(公告)日：2012-11-13

申请号：US12723922

申请日：2010-03-15

申请人： Takayuki Iwai ,  Shuso Fujii ,  Shinji Miyano

发明人： Takayuki Iwai ,  Shuso Fujii ,  Shinji Miyano

IPC分类号： G11C7/22

CPC分类号： G11C11/4076 ,  G11C11/4091 ,  G11C2207/2236

摘要： A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

摘要翻译： 读出放大器电路感测并放大从布置在字线和位线的交点处的存储单元读取的信号。 写入电路读取保存在存储单元的第一存储单元中的第一数据，并将与第一数据相对应的第二数据写入与第一存储单元不同的第二存储单元。 数据锁存电路保存从第一存储单元读取的数据。 逻辑运算电路使用从第二存储单元读取的数据和保存在数据锁存电路中的数据作为输入值进行逻辑运算，并输出第三数据作为运算值。 回写电路将第三数据写回第一存储单元。

公开(公告)号：US08035949B2

公开(公告)日：2011-10-11

申请号：US12391624

申请日：2009-02-24

申请人： Shinji Miyano

发明人： Shinji Miyano

IPC分类号： H02G1/00 ,  H01H47/00

CPC分类号： H02N1/006

摘要： A semiconductor device applies a hold voltage Vhold to an upper electrode of an electrostatic actuator and a ground voltage to a lower electrode. After the semiconductor device sets the voltage of the lower electrode to a test voltage Vtest, it eliminates the hold voltage Vhold from the upper electrode and places the voltage of the upper electrode in a high impedance state. The potential difference between the upper electrode and the lower electrode is set to Vhold−Vtest=Vmon. Thereafter, the voltage of the lower electrode is returned to the ground voltage. Whether the electrostatic actuator is placed in an open state or in a closed state is determined by measuring the capacitance between the electrodes based on the amount of drop of the voltage of the upper electrode due to capacitance coupling at the time. With this operation, the state of the electrostatic actuator can be simply and accurately determined, and when it is determined that charging and the like occur to the electrostatic actuator, it can be promptly returned to a normal operation state.

摘要翻译： 半导体器件向静电致动器的上电极施加保持电压Vhold，将接地电压施加到下电极。 在半导体器件将下电极的电压设定为测试电压Vtest之后，消除了来自上电极的保持电压Vhold，并将上电极的电压置于高阻抗状态。 上电极和下电极之间的电位差被设定为Vhold-Vtest = Vmon。 此后，下电极的电压返回接地电压。 静电致动器处于打开状态或处于闭合状态是通过基于由于电容耦合引起的上部电极的电压的下降量来测量电极之间的电容来确定的。 通过该动作，能够简单且准确地确定静电致动器的状态，并且当确定静电致动器发生充电等时，可以迅速恢复到正常工作状态。

公开(公告)号：US20110032778A1

公开(公告)日：2011-02-10

申请号：US12723922

申请日：2010-03-15

申请人： Takayuki Iwai ,  Shuso Fujii ,  Shinji Miyano

发明人： Takayuki Iwai ,  Shuso Fujii ,  Shinji Miyano

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C11/4076 ,  G11C11/4091 ,  G11C2207/2236

摘要： A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

摘要翻译： 读出放大器电路感测并放大从布置在字线和位线的交点处的存储单元读取的信号。 写入电路读取保存在存储单元的第一存储单元中的第一数据，并将与第一数据相对应的第二数据写入与第一存储单元不同的第二存储单元。 数据锁存电路保存从第一存储单元读取的数据。 逻辑运算电路使用从第二存储单元读取的数据和保存在数据锁存电路中的数据作为输入值进行逻辑运算，并输出第三数据作为运算值。 回写电路将第三数据写回第一存储单元。

公开(公告)号：US07263010B2

公开(公告)日：2007-08-28

申请号：US11194539

申请日：2005-08-02

申请人： Hitoshi Iwai ,  Shinji Miyano

发明人： Hitoshi Iwai ,  Shinji Miyano

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/72 ,  G11C2029/0405 ,  G11C2029/1208 ,  G11C2229/743 ,  G11C2229/746 ,  G11C2229/763 ,  G11C2229/766

摘要： A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a plurality of redundancy sections respectively provided for the plurality of memory blocks and configured to be substituted for defective memory cells, a test circuit that carries out a test on the memory cell array and outputs defective data, first and second memory circuit that temporarily store the defective data, a first write circuit that writes the defective data alternately in the first and second memory circuits, a first read circuit that reads the defective data alternately from the first and second memory circuits, a plurality of third memory circuits respectively provided for the plurality of memory blocks, that store the defective data, and a second write circuit that writes defective data read by the first read circuit in a third memory circuit corresponding to a memory block in which an error occurred.

摘要翻译： 一种半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，多个冗余部分，分别为多个存储器块提供并被配置为代替有缺陷的存储器单元;测试电路，对存储器进行测试 单元阵列并输出缺陷数据，临时存储缺陷数据的第一和第二存储器电路，将缺陷数据交替地写入第一和第二存储器电路的第一写入电路，从第一个存储器电路交替读取缺陷数据的第一读取电路 和第二存储器电路，分别为存储有缺陷数据的多个存储器块提供的多个第三存储器电路;以及第二写入电路，其将由第一读取电路读取的缺陷数据写入与存储器相对应的第三存储器电路中 阻塞发生错误。

公开(公告)号：US20070079218A1

公开(公告)日：2007-04-05

申请号：US11436600

申请日：2006-05-19

申请人： Takeshi Nagai ,  Shinji Miyano

发明人： Takeshi Nagai ,  Shinji Miyano

IPC分类号： G11C29/00

CPC分类号： G11C11/406 ,  G06F11/106 ,  G11C11/40615 ,  G11C2029/0411 ,  G11C2211/4062

摘要： When memory cells enter a data holding mode, a control circuit of a semiconductor memory device reads out a plurality of data from the memory cells to generate and store a check bit for error detection and correction, and performs a refresh operation in a period within an error occurrence allowable range of an error correcting operation performed by an ECC circuit by using the check bit. Before a normal operation mode is restored from the data holding mode, the control circuit performs control such that an error bit of the data is corrected by using the check bit. In an entry/exit period, read and write are performed by a page operation.

摘要翻译： 当存储器单元进入数据保持模式时，半导体存储器件的控制电路从存储器单元中读出多个数据，以生成并存储用于错误检测和校正的校验位，并且在 通过使用校验位由ECC电路进行的纠错操作的误差发生容许范围。 在从数据保持模式恢复正常操作模式之前，控制电路执行控制，使得通过使用校验位来校正数据的错误位。 在进入/退出期间，通过页面操作执行读取和写入。

公开(公告)号：US06601199B1

公开(公告)日：2003-07-29

申请号：US09405128

申请日：1999-09-24

申请人： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

发明人： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

IPC分类号： G01R3128

CPC分类号： G01R31/3167 ,  G01R31/318505 ,  Y10S257/909

摘要： A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.

摘要翻译： 多个存储器宏布置在半导体芯片中。 宏ID生成电路生成用于识别存储宏的宏ID，并具有不同的布局。 这些宏ID生成电路被布置在半导体芯片中的存储器宏之外，使得存储器宏中的测试控制块可以在所有存储器宏之间使用相同的布局来减少设计负载。

公开(公告)号：US6047344A

公开(公告)日：2000-04-04

申请号：US34218

申请日：1998-03-04

申请人： Atsushi Kawasumi ,  Shinji Miyano

发明人： Atsushi Kawasumi ,  Shinji Miyano

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/56 ,  G06F13/42 ,  G06F12/00 ,  H04L7/00

CPC分类号： G11C7/22

摘要： The practical operation speed of the memory device is increased by multiplexing input and output signals so as to increase the internal operation frequency higher than the external clock frequency. The feature of the memory device of the present invention is that it has the function of making the internal operation frequency higher than the external clock frequency by making the external bit width larger than the internal bit width, writing write data by dividing them successively by time division operation, into those having an internal bit width, and allocating read data to use an entire external bit width. According to the present invention, the practical operation speed of the memory device assembled on the board can be increased over the upper frequency limit of signals transmitted through the wiring on the board, and the high frequency performance of the memory device can be tested at the step of the die sorting test.

摘要翻译： 通过复用输入和输出信号来增加存储器件的实际操作速度，从而增加内部工作频率高于外部时钟频率。 本发明的存储器件的特征在于，通过使外部位宽度大于内部位宽，具有使内部工作频率高于外部时钟频率的功能，通过将写入数据依次除以时间来写入数据 分割为具有内部位宽的数据，并分配读取数据以使用整个外部位宽。 根据本发明，组装在电路板上的存储器件的实际操作速度可以在通过板上的布线传输的信号的上限频率上增加，并且存储器件的高频性能可以在 模具分选测试的一步。