公开(公告)号：US08322766B1

公开(公告)日：2012-12-04

申请号：US13287736

申请日：2011-11-02

Applicant: William Hsiung ,  Shih-Chun Lo ,  Tony Lin

Inventor： William Hsiung ,  Shih-Chun Lo ,  Tony Lin

IPC: B25J15/08

CPC classification number: H01L21/68707 ,  B25J11/0095 ,  B25J15/0475

Abstract: A gripper applied in a transport mechanism for transporting a wafer is provided. The transport mechanism includes a bar. The gripper includes a fixing member fixed to the bar, and a carrying member. The fixing member includes two grooves adjacent to the bottom of the fixing member. Each groove includes an entrance and a retaining portion. The carrying member includes a notch and a first claw. The notch is located at the top of the carrying member and communicates two opposite sides of the carrying member. The notch includes two inner walls, each having a protrusion. The carrying member is assembled to the fixing member by sliding each protrusion along one of the grooves from the corresponding entrance and until abutting against the corresponding retaining portion. The first claw is located at a first sidewall of the carrying member. The edge of the wafer is supportable by the first claw.

Abstract translation: 提供了应用于输送晶片的输送机构中的夹持器。 运输机构包括一个酒吧。 夹持器包括固定到杆的固定构件和承载构件。 固定构件包括与固定构件的底部相邻的两个凹槽。 每个凹槽包括入口和保持部分。 承载构件包括凹口和第一爪。 凹口位于承载构件的顶部并且连通承载构件的两个相对的两侧。 凹口包括两个内壁，每个具有突出部。 通过沿着相应的入口沿着一个凹槽滑动每个突起并且直到抵靠相应的保持部分而将承载构件组装到固定构件。 第一爪位于承载构件的第一侧壁处。 晶片的边缘可由第一爪支撑。

公开(公告)号：USD652186S1

公开(公告)日：2012-01-10

申请号：US29369918

申请日：2010-09-15

Applicant: Tony Lin

Designer： Tony Lin

公开(公告)号：US20110175413A1

公开(公告)日：2011-07-21

申请号：US12689731

申请日：2010-01-19

Applicant: Tony Lin

Inventor： Tony Lin

IPC: A47C3/03

CPC classification number: A47C3/03

Abstract: A locking mechanism for a glider rocker having a gliding chair seat mounted on a stationary base, including an operating assembly mounted on the gliding chair seat, a pair of bearing brackets mounted on the stationary base respectively, and a pair of mounting assemblies. Each mounting assembly includes a prop, a strut, a curved elongated member, a mounting bracket, and a restoring spring connected with the curved elongated member and the prop.

Abstract translation: 一种用于滑翔机摇杆的锁定机构，其具有安装在固定基座上的滑翔椅座椅，其包括安装在滑动椅座上的操作组件，分别安装在固定基座上的一对轴承座和一对安装组件。 每个安装组件包括支柱，支柱，弯曲的细长构件，安装支架和与弯曲的细长构件和支柱连接的复原弹簧。

公开(公告)号：US07193624B2

公开(公告)日：2007-03-20

申请号：US10720432

申请日：2003-11-24

Applicant: Tony Lin

Inventor： Tony Lin

IPC: G09G5/00 ,  G06F1/26

CPC classification number: H02J9/005 ,  G09G3/00 ,  G09G2330/02 ,  G09G2330/021

Abstract: A power control unit of a display apparatus includes an AC-to-DC converter for receiving an external AC power. A regulator receives a DC output from the converter, and is operable in one of an enabled state of outputting a target DC power when receiving a first level signal, and a disabled state of not outputting the target DC power when receiving a second level signal. An electronic switch is operable for switching from an OFF-mode, where a processor permits a delay circuit to output the second level signal to the regulator, to an ON-mode, where the electronic switch initially enables the delay circuit to output the first level signal to the regulator such that the processor receives the target DC power from the regulator and where the electronic switch outputs a trigger signal to the processor so as to enable the processor to latch the first level signal and to provide the target DC power to a display module.

Abstract translation: 显示装置的电源控制单元包括用于接收外部AC电力的AC-DC转换器。 调节器从转换器接收DC输出，并且在接收到第一电平信号时可以在输出目标DC电力的使能状态中的一个中工作，以及当接收到第二电平信号时不输出目标DC电力的禁止状态。 电子开关可操作用于从处于允许延迟电路将第二电平信号输出到调节器的OFF模式切换到ON模式，其中电子开关最初使能延迟电路输出第一电平 信号到调节器，使得处理器从调节器接收目标DC电力，并且其中电子开关向处理器输出触发信号，以使得处理器能够锁存第一电平信号并向显示器提供目标DC电力 模块。

公开(公告)号：US20060038261A1

公开(公告)日：2006-02-23

申请号：US11258491

申请日：2005-10-24

Applicant: Yoyi Gong ,  Tony Lin ,  Jung-Tsung Tseng ,  Abula Yu

Inventor： Yoyi Gong ,  Tony Lin ,  Jung-Tsung Tseng ,  Abula Yu

IPC: H01L29/06

CPC classification number: H01L21/76224

Abstract: A shallow trench isolation (STI) structure and fabricating method thereof is provided. A substrate is provided. A patterned mask layer is formed over the substrate. Using the patterned mask layer as an etching mask, the substrate is patterned to form a trench. A nitridation process is performed to form a silicon nitride liner on the surface of the trench. An insulating material is deposited to fill the trench. Since the silicon nitride liner within the STI is very thin, residual stress within the substrate is reduced, and the silicon nitride liner has very little or negligible impact on the trench aspect ratio.

Abstract translation: 提供浅沟槽隔离（STI）结构及其制造方法。 提供基板。 在衬底上形成图案化掩模层。 使用图案化掩模层作为蚀刻掩模，将衬底图案化以形成沟槽。 进行氮化处理以在沟槽的表面上形成氮化硅衬垫。 沉积绝缘材料以填充沟槽。 由于STI内的氮化硅衬垫非常薄，衬底内的残余应力减小，并且氮化硅衬垫对沟槽纵横比的影响很小或可忽略不计。

公开(公告)号：US06654841B2

公开(公告)日：2003-11-25

申请号：US09904905

申请日：2001-07-16

Applicant: Tony Lin

Inventor： Tony Lin

IPC: G06F1300

CPC classification number: H05K5/0278

Abstract: A USB interface flash memory card reader is attached with a built-in flash memory so that the card reader itself provides a function of data storage in addition to a function of reading data in a flash memory card or writing data into the flash memory card.

公开(公告)号：US06559016B2

公开(公告)日：2003-05-06

申请号：US09733822

申请日：2000-12-05

Applicant: Hua-Chou Tseng ,  Tony Lin

Inventor： Hua-Chou Tseng ,  Tony Lin

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped, high-energy implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavily doped implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. A deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.

公开(公告)号：US06200870B1

公开(公告)日：2001-03-13

申请号：US09189355

申请日：1998-11-09

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/28061 ,  H01L21/28247

Abstract: A method for forming a gate that improves the quality of the gate includes sequentially forming a gate oxide layer, a polysilicon layer, a conductive layer and a masking layer on a substrate. Thereafter, the masking layer, the conductive layer, the polysilicon layer and the gate oxide layer are patterned to form the gate. Then, a passivation layer, for increasing the thermal stability and the chemical stability of the gate, is formed on the sidewall of the conductive layer by ion implantation with nitrogen cations. The nitrogen cations are doped into the substrate, under the gate oxide layer, by ion implantation, which can improve the penetration of the phosphorus ions.

Abstract translation: 用于形成提高栅极质量的栅极的方法包括在衬底上顺序地形成栅极氧化物层，多晶硅层，导电层和掩模层。 此后，对掩模层，导电层，多晶硅层和栅极氧化物层进行图案化以形成栅极。 然后，通过用氮阳离子的离子注入，在导电层的侧壁上形成用于增加栅极的热稳定性和化学稳定性的钝化层。 氮阳离子通过离子注入在栅极氧化物层下方掺杂到衬底中，这可以改善磷离子的渗透。

公开(公告)号：US06174791B1

公开(公告)日：2001-01-16

申请号：US09276294

申请日：1999-03-25

Applicant: Tony Lin ,  Jih-Wen Chou ,  C. C. Hsue

Inventor： Tony Lin ,  Jih-Wen Chou ,  C. C. Hsue

IPC: H01L21425

CPC classification number: H01L21/28518 ,  H01L21/26506 ,  H01L29/665

Abstract: A method for forming an amorphous silicon layer over the terminals of a MOS transistor. The method includes the steps of forming a mask layer having an opening that exposes the gate polysilicon layer over the MOS transistor. Next, using the mask layer as a mask, an inactive ion implant operation is carried out such that inactive ions are implanted into the gate polysilicon layer. Thereafter, again using the mask layer as a mask, a first heavy bombarding operation is carried out, implanting ions locally. Finally, the mask layer is removed and then a second heavy bombarding operation is carried out, implanting ions globally.

Abstract translation: 一种用于在MOS晶体管的端子上形成非晶硅层的方法。 该方法包括以下步骤：形成具有在MOS晶体管上暴露栅极多晶硅层的开口的掩模层。 接下来，使用掩模层作为掩模，执行非活性离子注入操作，使得非活性离子注入到栅极多晶硅层中。 此后，再次使用掩模层作为掩模，进行第一次重轰击操作，局部注入离子。 最后，去除掩模层，然后进行第二次重轰击操作，全局注入离子。

公开(公告)号：US06165857A

公开(公告)日：2000-12-26

申请号：US469008

申请日：1999-12-21

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/417

CPC classification number: H01L29/6659 ,  H01L21/28052 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: A new improvement for selective epitaxial growth is disclosed. In one embodiment, the present invention provides a low power metal oxide semiconductor field effect transistor (MOSFET), which includes a substrate. Next, a gate oxide layer is formed on the substrate. Moreover, a polysilicon layer is deposited on the gate oxide layer. Patterning to etch the polysilicon layer and the gate oxide layer to define a gate. First ions are implanted into the substrate by using said gate as a hard mask. Sequentially, a liner oxide is covered over the entire exposed surface of the resulting structure. Moreover, a conformal first dielectric layer and second dielectric layer are deposited above the liner oxide in proper order. The second dielectric layer is etched back to form a dielectric spacer on sidewall of the first dielectric layer. Next, the first dielectric layer is etched until upper surface of the gate and a portion of the substrate are exposed, wherein a part of the second dielectric layer is also etched accompanying with etching a part of the first dielectric layer. Further, second ions are implanted into the exposed substrate to form a source/drain region. A conductive layer is selectively formed on said over the exposed gate and source/drain. Finally, a self-aligned silicide layer is formed over the conductive layer.

Abstract translation: 公开了选择性外延生长的新改进。 在一个实施例中，本发明提供一种包括衬底的低功率金属氧化物半导体场效应晶体管（MOSFET）。 接着，在基板上形成栅极氧化层。 此外，在栅极氧化物层上沉积多晶硅层。 图案化以蚀刻多晶硅层和栅极氧化物层以限定栅极。 通过使用所述栅极作为硬掩模将第一离子注入到衬底中。 接下来，衬垫氧化物覆盖在所得结构的整个暴露表面上。 此外，适形的第一介电层和第二介电层以适当的顺序沉积在衬垫氧化物的上方。 回蚀第二电介质层以在第一电介质层的侧壁上形成电介质间隔物。 接下来，蚀刻第一电介质层直到栅极的上表面和衬底的一部分被暴露，其中第二电介质层的一部分也被蚀刻，同时蚀刻第一介电层的一部分。 此外，将第二离子注入暴露的衬底中以形成源/漏区。 在暴露的栅极和源极/漏极上的选择性地形成导电层。 最后，在导电层上形成自对准的硅化物层。