公开(公告)号：US20070259503A1

公开(公告)日：2007-11-08

申请号：US11777291

申请日：2007-07-13

Applicant: Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

Inventor： Hui-Chen Chang ,  Tony Lin ,  Brook Hsu ,  Cyrus LW Chen ,  Meng-Lin Lee ,  Wei-Tsun Shiau

IPC: H01L21/336

CPC classification number: H01L21/28114 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor device is provided herein. The semiconductor device includes a substrate, a gate dielectric layer, a gate, a pair of source/drain regions and a stressed layer. The gate dielectric layer is disposed on the substrate and the gate whose top area is larger than its bottom area is disposed on the gate dielectric layer. The source/drain regions are disposed in the substrate next to the sidewalls of the gate. The stressed layer is disposed on the substrate to cover the gate and the source/drain regions.

Abstract translation: 本发明提供一种制造半导体器件的方法。 半导体器件包括衬底，栅介质层，栅极，一对源/漏区和应力层。 栅极电介质层设置在基板上，并且顶部区域大于其底部区域的栅极设置在栅极介电层上。 源极/漏极区域设置在邻近栅极的侧壁的衬底中。 应力层设置在基板上以覆盖栅极和源极/漏极区域。

公开(公告)号：US20060047811A1

公开(公告)日：2006-03-02

申请号：US10932569

申请日：2004-09-01

Applicant: Daniel Lau ,  Daniel Crevier ,  Jorge Morinigo ,  Robert Vreeland ,  Shengyong Li ,  Stuart DeSpain ,  Brooke Nelson ,  Jeffrey Smith ,  James Grandy ,  Laura Neumann ,  Tony Lin ,  Vianna Tam

Inventor： Daniel Lau ,  Daniel Crevier ,  Jorge Morinigo ,  Robert Vreeland ,  Shengyong Li ,  Stuart DeSpain ,  Brooke Nelson ,  Jeffrey Smith ,  James Grandy ,  Laura Neumann ,  Tony Lin ,  Vianna Tam

IPC: G06F15/173

CPC classification number: H04L67/2852 ,  H04L51/16

Abstract: Described is a system and method that enables project management across application programs, including an email program, calendar program, spreadsheet program, word processing program, note taking program and others. A central project-related view provides access to project-related data items and may display a schedule, a task list of tasks filtered as being relevant to a project, a note page related to a project, and emails relevant to the project. In addition, other application objects (file, documents, presentations and spreadsheets) are also captured in the view and presented for easy access. Metadata including a project identifier is maintained in a database for the various data items, allowing rapid location of the data items related to a project via query techniques. A project palette allows access to the items from within another application program, and a project gallery allows a user alternative access to the files related to a project.

Abstract translation: 描述了一种能够跨应用程序进行项目管理的系统和方法，包括电子邮件程序，日历程序，电子表格程序，文字处理程序，记录程序等。 中央项目相关视图提供对项目相关数据项的访问，并且可以显示计划，过滤为与项目相关的任务的任务列表，与项目相关的注释页面以及与项目相关的电子邮件。 此外，其他应用对象（文件，文档，演示文稿和电子表格）也被捕获在视图中并被呈现以便于访问。 包含项目标识符的元数据被保存在用于各种数据项的数据库中，允许通过查询技术快速定位与项目相关的数据项。 项目调色板允许访问另一个应用程序中的项目，项目库允许用户对与项目相关的文件进行替代访问。

公开(公告)号：US20050110787A1

公开(公告)日：2005-05-26

申请号：US10720432

申请日：2003-11-24

Applicant: Tony Lin

Inventor： Tony Lin

IPC: G09G3/00 ,  G09G5/00 ,  H02J9/00

CPC classification number: H02J9/005 ,  G09G3/00 ,  G09G2330/02 ,  G09G2330/021

Abstract: A power control unit of a display apparatus includes an AC-to-DC converter for receiving an external AC power. A regulator receives a DC output from the converter, and is operable in one of an enabled state of outputting a target DC power when receiving a first level signal, and a disabled state of not outputting the target DC power when receiving a second level signal. An electronic switch is operable for switching from an OFF-mode, where a processor permits a delay circuit to output the second level signal to the regulator, to an ON-mode, where the electronic switch initially enables the delay circuit to output the first level signal to the regulator such that the processor receives the target DC power from the regulator and where the electronic switch outputs a trigger signal to the processor so as to enable the processor to latch the first level signal and to provide the target DC power to a display module.

Abstract translation: 显示装置的电源控制单元包括用于接收外部AC电力的AC-DC转换器。 调节器从转换器接收DC输出，并且在接收到第一电平信号时可以在输出目标DC电力的使能状态中的一个中工作，以及当接收到第二电平信号时不输出目标DC电力的禁止状态。 电子开关可操作用于从处于允许延迟电路将第二电平信号输出到调节器的OFF模式切换到ON模式，其中电子开关最初使能延迟电路输出第一电平 信号到调节器，使得处理器从调节器接收目标DC电力，并且其中电子开关向处理器输出触发信号，以使得处理器能够锁存第一电平信号并向显示器提供目标DC电力 模块。

公开(公告)号：US06605005B1

公开(公告)日：2003-08-12

申请号：US10198084

申请日：2002-07-19

Applicant: Tony Lin

Inventor： Tony Lin

IPC: A63B6936

CPC classification number: A63B69/3614 ,  A63B69/3632 ,  A63B69/3676 ,  A63B69/3685 ,  A63B2071/0694

Abstract: A detachable laser pointer is constructed to include a mounting base, the mounting base having a smoothly arched rear coupling groove for coupling to the shaft of a golf putter and a locating plate of C-shaped cross section upwardly extended from the smoothly arched coupling groove for plugging in between the shaft and grip of the golf putter and a front receiving groove, a joint rotatably coupled to the receiving groove, a laser module pivoted to the joint and adapted for emitting a laser beam to aim the putter head of the golf putter to the hole.

Abstract translation: 可拆卸的激光指示器被构造成包括安装基座，该安装基座具有平滑拱形的后连接槽，用于联接到高尔夫推杆的轴上，以及从平滑的拱形联接槽向上延伸的C形横截面的定位板，用于 插入高尔夫推杆的轴和把手之间以及前接收槽，可旋转地联接到接收槽的接头，激光模块，其枢转到接头并适于发射激光束以使高尔夫推杆的推杆头对准 那个洞。

公开(公告)号：US06190981B1

公开(公告)日：2001-02-20

申请号：US09243740

申请日：1999-02-03

Applicant: Tony Lin ,  Jih-Wen Chou

Inventor： Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/665

Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.

Abstract translation: 描述了制造金属氧化物半导体晶体管的方法。 提供其上具有隔离结构的基板。 在衬底上形成栅氧化层。 在栅氧化层上形成多晶硅层。 图案化多晶硅层以在栅极氧化物层上形成栅极。 在门的侧壁上形成偏移间隔物。 通过离子注入在栅极两侧的衬底中形成源极/漏极延伸。 绝缘间隔件形成在偏移间隔件的侧壁上。 通过使用栅极，偏移间隔物和绝缘间隔物作为掩模的离子注入在衬底中形成源极/漏极区。 在栅极和源极/漏极区域的表面上形成硅化物。 在形成自对准硅胶后，去除偏移间隔物。 在去除偏移间隔物之后，通过离子注入在源极/漏极延伸部下方的衬底中形成光晕掺杂区域。

公开(公告)号：US06171939B2

公开(公告)日：2001-01-09

申请号：US09348389

申请日：1999-07-07

Applicant: Tony Lin

Inventor： Tony Lin

IPC: H01L213205

CPC classification number: H01L21/28052 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665

Abstract: A method for forming a polysilicon gate electrode. A semiconductor is provided. A gate oxide layer, a partially doped polysilicon layer and an undoped polysilicon are sequentially formed over the semiconductor substrate. The undoped polysilicon layer, the partially doped polysilicon layer and the gate oxide layer are patterned to form a gate electrode.

Abstract translation: 一种形成多晶硅栅电极的方法。 提供半导体。 在半导体衬底上依次形成栅氧化层，部分掺杂多晶硅层和未掺杂多晶硅。 对未掺杂的多晶硅层，部分掺杂的多晶硅层和栅极氧化物层进行构图以形成栅电极。

公开(公告)号：US6117743A

公开(公告)日：2000-09-12

申请号：US203023

申请日：1998-12-01

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Coming Chen

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Coming Chen

IPC: H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/66575 ,  H01L21/0276 ,  H01L21/28061 ,  H01L21/28123 ,  H01L29/4941 ,  H01L29/66545 ,  Y10S438/952

Abstract: A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer. Finally, a chemical-mechanical polishing operation is carried out to planarize the conductive layer, retaining only the conductive layer above the polysilicon layer.

Abstract translation: 一种制造MOS器件的方法，包括以下步骤：提供在其上具有器件隔离结构的半导体衬底，然后在衬底上依次沉积栅极氧化物层，多晶硅层和抗反射涂层。 接下来，栅极结构从栅极氧化物层，多晶硅层和抗反射涂层构图。 然后，在栅极结构的侧壁上形成间隔物。 此后，在源极/漏极区域上形成金属硅化物层。 之后，在栅极结构和整个衬底上形成层间介电层（ILD）层。 然后，层间电介质层被平坦化以暴露抗反射涂层。 接下来，去除防反射涂层，然后在层间电介质层和多晶硅层上沉积阻挡层。 随后，在阻挡层上沉积导电层。 最后，进行化学机械抛光操作以使导电层平坦化，仅在多晶硅层上保留导电层。

公开(公告)号：US6025241A

公开(公告)日：2000-02-15

申请号：US73576

申请日：1998-05-06

Applicant: Tony Lin ,  Water Lur

Inventor： Tony Lin ,  Water Lur

IPC: H01L21/3115 ,  H01L21/336 ,  H01L21/28

CPC classification number: H01L29/66507 ,  H01L29/6659 ,  H01L21/31155 ,  Y10S148/147

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer. Through this method, the resultant semiconductor device is reliable in operation since the drawback of the occurrence of leakage current or short-circuit that could be otherwise resulted between the self-aligned silicide and the substrate owing to the short-channel effect can be eliminated. Moreover, the resultant semiconductor device has increased anti-static capability that can protect the semiconductor device against electro-static damage.

Abstract translation: 提供了一种用于制造具有自对准硅化物的半导体器件（例如MOS（金属氧化物半导体）晶体管）的方法。 该方法可以防止硅化物与衬底之间的结漏电，从而使所得的半导体器件具有可靠的性能。 该方法包括制备半导体衬底的步骤; 在所述衬底上形成至少一个晶体管元件，所述晶体管元件包括一对源极/漏极区域，栅极，所述栅极上的电介质层以及所述栅极侧壁上的间隔物; 并且进行离子轰击处理，以将邻近间隔物顶部的电介质层的一部分输送到间隔物的底部旁边。 通过该方法，由于短沟道效应，可以消除由于短路导致的自对准硅化物和衬底之间的漏电流或短路的缺点，所以得到的半导体器件工作可靠。 此外，所得到的半导体器件具有增强的抗静电能力，可以保护半导体器件免受静电损坏。

公开(公告)号：US6015741A

公开(公告)日：2000-01-18

申请号：US59428

申请日：1998-04-13

Applicant: Tony Lin ,  Water Lur ,  Shih-Wei Sun

Inventor： Tony Lin ,  Water Lur ,  Shih-Wei Sun

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/44

CPC classification number: H01L21/76897 ,  H01L29/665

Abstract: A method for forming a self-aligned contact window such that the method is compatible with the process of forming a self-aligned titanium silicide layer on the same device, and hence capable of miniaturizing device dimensions. Furthermore, this invention utilizes the thicker etching stop layer thickness above the gate region than above the source/drain region to protect the titanium silicide layer in the gate region against electrical contact with the self-aligned contact.

Abstract translation: 一种用于形成自对准接触窗的方法，使得该方法与在同一器件上形成自对准钛硅化物层的工艺兼容，因此能够使器件尺寸小型化。 此外，本发明利用栅极区域之上的栅极区域之上的厚度超过源极/漏极区域的厚度，以保护栅极区域中的硅化钛层免受与自对准接触件的电接触。

公开(公告)号：US6001738A

公开(公告)日：1999-12-14

申请号：US62115

申请日：1998-04-17

Applicant: Tony Lin ,  Water Lur ,  Shih-Wei Sun

Inventor： Tony Lin ,  Water Lur ,  Shih-Wei Sun

IPC: H01L21/336 ,  H01L21/283

CPC classification number: H01L29/6659 ,  H01L29/665

Abstract: A method of forming salicide, of which the characteristics is the formation of a silicon nitride layer before the source/drain being implanted with dopant. The silicon nitride layer avoid the oxygen within the oxide layer to implant into the source/drain. Thus, a better salicide is obtained. In addition, the formation of the parasitic spacers made of silicon nitride at the side wall bottom of the gate spacer increases the distance between the salicide and the junction. Consequently, the leakage current is prevented. While the silicon nitride layer is removed, the polysilicon of gate and the silicon of the source/drain are amorphized. This is advantageous to the formation of salicide without the step of ion implantation.

Abstract translation: 一种形成硅化物的方法，其特征是在掺杂有掺杂剂的源极/漏极之前形成氮化硅层。 氮化硅层避免氧化物层内的氧气注入到源极/漏极中。 因此，获得更好的自杀剂。 此外，在栅极间隔物的侧壁底部由氮化硅制成的寄生间隔物的形成增加了自对准硅化物与接合部之间的距离。 因此，防止漏电流。 当去除氮化硅层时，栅极和源极/漏极的硅的多晶硅是非晶化的。 这对于没有离子注入步骤的硅化物的形成是有利的。