公开(公告)号：US08209446B2

公开(公告)日：2012-06-26

申请号：US13221622

申请日：2011-08-30

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20110314186A1

公开(公告)日：2011-12-22

申请号：US13221622

申请日：2011-08-30

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20110307759A1

公开(公告)日：2011-12-15

申请号：US13216411

申请日：2011-08-24

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F11/08 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US20110010504A1

公开(公告)日：2011-01-13

申请号：US12500747

申请日：2009-07-10

申请人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

发明人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

摘要翻译： 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

公开(公告)号：US07804721B2

公开(公告)日：2010-09-28

申请号：US12487035

申请日：2009-06-18

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： G11C7/10 ,  G06F3/00 ,  G06F5/00 ,  G06F13/36

CPC分类号： G06F5/065

摘要： In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write control logic. The queue is configured to store a plurality of data items, wherein each data item has a type which is one of a plurality of types of data items that can be stored in the queue. The write control logic is configured to maintain write pointers that identify entries in the queue for each of the plurality of types. The write control logic is configured to update the write pointer corresponding to an input type for an input data item written to the queue. Additionally, the write control logic is configured to enqueue a write event in the FIFO to transport the enqueue event to a read clock domain different from the write clock domain.

摘要翻译： 在一个实施例中，一种装置包括队列，耦合到队列的写入控制逻辑，并且可在写入时钟域中操作，以及耦合到写入控制逻辑的先入先出缓冲器（FIFO）。 队列被配置为存储多个数据项，其中每个数据项具有可以存储在队列中的多种类型的数据项之一的类型。 写入控制逻辑被配置为维护写入指针，其针对多种类型中的每一种来标识队列中的条目。 写控制逻辑被配置为更新对应于写入队列的输入数据项的输入类型的写指针。 此外，写入控制逻辑被配置为对FIFO中的写入事件进行排队，以将入站事件传送到与写入时钟域不同的读取时钟域。

公开(公告)号：US20100165842A1

公开(公告)日：2010-07-01

申请号：US12344949

申请日：2008-12-29

申请人： James Wang ,  Zongjian Chen

发明人： James Wang ,  Zongjian Chen

IPC分类号： H04L12/24

CPC分类号： G06F13/385 ,  H04L47/10 ,  H04L47/39 ,  H04L49/90

摘要： In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.

摘要翻译： 在一个实施例中，基于信用的流量控制接口上的接收器被配置为在接收到数据有效载荷时释放一个或多个数据信息，该数据有效载荷在缓冲存储器内产生更少的未被使用的数据信用，该缓冲存储器以比该 数据信用。 在另一个实施例中，基于实际分组数据有效载荷大小动态地调整报头信用和数据信用。

公开(公告)号：US07620746B2

公开(公告)日：2009-11-17

申请号：US11238850

申请日：2005-09-29

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Weichun Ku

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括发射控制电路，卸载引擎和接收控制电路。 发送控制电路被配置为从主机中的地址空间读取第一DMA数据。 耦合以从发送控制电路接收第一DMA数据，卸载引擎被配置为对第一DMA数据执行至少第一操作以产生结果。 卸载引擎被配置为在向卸载引擎提供第一DMA数据的DMA传送期间至少开始执行第一操作。 耦合到卸载引擎以接收结果，接收控制电路被配置为根据描述DMA传输的DMA描述符数据结构将结果写入主机中的地址空间。

公开(公告)号：US07496695B2

公开(公告)日：2009-02-24

申请号：US11238790

申请日：2005-09-29

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20070073922A1

公开(公告)日：2007-03-29

申请号：US11238790

申请日：2005-09-29

申请人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

公开(公告)号：US08392658B2

公开(公告)日：2013-03-05

申请号：US12500768

申请日：2009-07-10

申请人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

发明人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC分类号： G06F12/00

CPC分类号： G06F12/128 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/123

摘要： In an embodiment, a cache stores tags for cache blocks stored in the cache. Each tag may include an indication identifying which of two or more replacement policies supported by the cache is in use for the corresponding cache block, and a replacement record indicating the status of the corresponding cache block in the replacement policy. Requests may include a replacement attribute that identifies the desired replacement policy for the cache block accessed by the request. If the request is a miss in the cache, a cache block storage location may be allocated to store the corresponding cache block. The tag associated with the cache block storage location may be updated to include the indication of the desired replacement policy, and the cache may manage the block in accordance with the policy. For example, in an embodiment, the cache may support both an LRR and an LRU policy.

摘要翻译： 在一个实施例中，高速缓存存储存储在高速缓存中的高速缓存块的标签。 每个标签可以包括标识由高速缓存支持的两个或多个替换策略中哪一个正在用于对应的高速缓存块的指示，以及指示替换策略中对应的高速缓存块的状态的替换记录。 请求可以包括标识用于请求访问的高速缓存块的期望替换策略的替换属性。 如果请求是高速缓存中的错过，则可以分配高速缓存块存储位置以存储对应的高速缓存块。 与高速缓存块存储位置相关联的标签可以被更新以包括期望的替换策略的指示，并且高速缓存可以根据策略来管理块。 例如，在一个实施例中，高速缓存可以支持LRR和LRU策略。