公开(公告)号：US09847428B1

公开(公告)日：2017-12-19

申请号：US15230496

申请日：2016-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/78648 ,  H01L29/41733 ,  H01L29/7869 ,  H01L29/78696

Abstract: An oxide semiconductor device includes an oxide semiconductor transistor including a first gate electrode, a second gate electrode, a third gate electrode, a first oxide semiconductor channel layer, a second oxide semiconductor channel layer, and two source/drain electrodes. The second gate electrode is disposed above the first gate electrode. The third gate electrode is disposed above the second gate electrode. At least a part of the first oxide semiconductor channel layer is disposed between the first gate electrode and the second gate electrode. At least a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and the third gate electrode. At least a part of each source/drain electrode is disposed between the first oxide semiconductor channel layer and the second oxide semiconductor channel layer. Each source/drain electrode contacts the first oxide semiconductor channel layer and the second oxide semiconductor channel layer.

公开(公告)号：US20170358582A1

公开(公告)日：2017-12-14

申请号：US15180095

申请日：2016-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen

IPC: H01L27/108 ,  H01L49/02 ,  H01L23/528 ,  H01L29/423 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/10814 ,  H01L23/528 ,  H01L27/10897 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/42356 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor array, the semiconductor memory array includes bit lines, word lines and memory cells. The bit lines are arranged in parallel in a first direction, and the word lines are arranged in parallel in a second direction which is different from the first direction. The memory cells are arranged in an array and electrically connected to corresponding bit lines and word lines respectively, and any two memory cells adjacent to each other share a same oxide semiconductor layer as a channel layer. The present invention also relates to a semiconductor memory device including two memory cells sharing a same oxide semiconductor layer as a channel layer.

公开(公告)号：US20170338351A1

公开(公告)日：2017-11-23

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Chen-Bin Lin ,  SANPO WANG ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

公开(公告)号：US09666491B1

公开(公告)日：2017-05-30

申请号：US15185007

申请日：2016-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L21/8256 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L49/02 ,  H01L21/477 ,  H01L21/428 ,  H01L29/40

CPC classification number: H01L21/8256 ,  H01L21/428 ,  H01L21/477 ,  H01L21/8258 ,  H01L23/5283 ,  H01L24/19 ,  H01L27/0629 ,  H01L27/0694 ,  H01L27/088 ,  H01L28/40 ,  H01L29/401 ,  H01L29/66969

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a first transistor is formed on a first surface of a substrate. Next, a thinning process is performed on the second surface of the substrate which is opposite to the first surface, to form a third surface. Then, a second transistor is formed on the third surface, in which the second transistor and the first transistor are electrically connected to each other through a through-silicon via penetrating through the first surface and the third surface.