公开(公告)号：US20220416068A1

公开(公告)日：2022-12-29

申请号：US17897237

申请日：2022-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a P-type III-V composition layer, a gate electrode and a carbon containing layer. The P-type III-V composition layer is disposed on the substrate, and the gate electrode is disposed on the P-type III-V composition layer. The carbon containing layer is disposed under the P-type III-V composition layer to function like an out diffusion barrier for preventing from the dopant within the P-type III-V composition layer diffusing into the stacked layers underneath during the annealing process.

公开(公告)号：US20220344474A1

公开(公告)日：2022-10-27

申请号：US17334837

申请日：2021-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

Abstract: A superlattice structure includes a substrate. A first superlattice stack is disposed on the substrate. The first superlattice stack includes a first superlattice layer, a second superlattice layer and a third superlattice layer disposed from bottom to top. Three stress relaxation layers respectively disposed between the first superlattice layer and the second superlattice layer, the second superlattice layer and the third superlattice layer and on the third superlattice layer. Each of the stress relaxation layers includes a group III-V compound layer. The thickness of each of the stress relaxation layers should be greater than a relaxation critical thickness.

公开(公告)号：US20220262942A1

公开(公告)日：2022-08-18

申请号：US17735100

申请日：2022-05-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/267 ,  H01L29/15 ,  H01L29/20

Abstract: An HEMT includes an aluminum gallium nitride layer. A gallium nitride layer is disposed below the aluminum gallium nitride layer. A zinc oxide layer is disposed under the gallium nitride layer. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer and between the drain electrode and the source electrode.

公开(公告)号：US20210134957A1

公开(公告)日：2021-05-06

申请号：US16708448

申请日：2019-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US20180097110A1

公开(公告)日：2018-04-05

申请号：US15281993

申请日：2016-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Mu Yang ,  Kuang-Hsiu Chen ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Yu-Ming Hsu ,  Fu-Cheng Yen ,  Chung-Min Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02057 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor structure comprises the following steps. First, a recess is formed in a substrate. At least one wet cleaning process is performed to the recess and the substrate. Then, a baking process is performed to the recess and the substrate in an atmosphere containing H2 gas. After the baking process, a dry cleaning process is performed the recess and the substrate.

公开(公告)号：US09847393B2

公开(公告)日：2017-12-19

申请号：US15286541

申请日：2016-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Sheng-Hsu Liu ,  Chieh-Lung Wu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/24 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/24 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.

公开(公告)号：US20170133470A1

公开(公告)日：2017-05-11

申请号：US15286541

申请日：2016-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Chun-Liang Kuo ,  Tsang-Hsuan Wang ,  Sheng-Hsu Liu ,  Chieh-Lung Wu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/24 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate, a gate structure on the substrate, a spacer adjacent to the gate structure, an epitaxial layer in the substrate adjacent to two sides of the spacer, and a dislocation embedded within the epitaxial layer. Preferably, the top surface of the epitaxial layer is lower than the top surface of the substrate, and the top surface of the epitaxial layer has a V-shape.