ADAPTIVE CPU NUMA SCHEDULING
    31.
    发明申请

    公开(公告)号:US20190205155A1

    公开(公告)日:2019-07-04

    申请号:US16292502

    申请日:2019-03-05

    Applicant: VMware, Inc.

    Abstract: Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to physical processors are provided. A CPU scheduler evaluates the latency between various candidate processors and the memory associated with the vCPU, and the size of the working set of the associated memory, and the vCPU scheduler selects an optimal processor for execution of a vCPU based on the expected memory access latency and the characteristics of the vCPU and the processors. The systems and methods further provide for monitoring system characteristics and rescheduling the vCPUs when other placements provide improved performance and efficiency.

    APPLICATION FAULT TOLERANCE VIA BATTERY-BACKED REPLICATION OF VOLATILE STATE

    公开(公告)号:US20190129814A1

    公开(公告)日:2019-05-02

    申请号:US15881480

    申请日:2018-01-26

    Applicant: VMware, Inc.

    Abstract: Techniques for implementing application fault tolerance via battery-backed replication of volatile state are provided. In one set of embodiments, a primary host system can detect a failure that causes an application of the primary host system to stop running. In response to detecting the failure, the primary host system can replicate volatile state that is used by the application to a secondary host system, where the secondary host system maintains a copy of the application, and where execution of the application is failed over to the copy on the secondary host system using the replicated volatile state.

    COMMIT COALESCING FOR MICRO-JOURNAL BASED TRANSACTION LOGGING

    公开(公告)号:US20170344595A1

    公开(公告)日:2017-11-30

    申请号:US15192937

    申请日:2016-06-24

    Applicant: VMware, Inc.

    CPC classification number: G06F16/2343 G06F16/2358 G06F16/2379

    Abstract: Techniques for using commit coalescing when performing micro-journal-based transaction logging are provided. In one embodiment a computer system can maintain, in a volatile memory, a globally ascending identifier, a first list of free micro-journals, and a second list of in-flight micro-journals. The computer system can further receive a transaction comprising a plurality of modifications to data or metadata stored in the byte-addressable persistent memory, select a micro-journal from the first list, obtain a lock on the globally ascending identifier, write a current value of the globally ascending identifier as a journal commit identifier into a header of the micro-journal, and write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction. The computer system can then commit the micro-journal to the byte-addressable persistent memory, increment the current value of the globally ascending identifier, and release the lock.

Patent Agency Ranking