公开(公告)号：US5990561A

公开(公告)日：1999-11-23

申请号：US97318

申请日：1998-06-12

申请人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L2924/0002

摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

摘要翻译： 根据本发明的使用钨丝塞的集成电路胶层的制造方法包括：（A）提供具有表面，中心，边缘和与该表面垂直的方向的基板; 和（B）在衬底的表面上溅射沉积胶层，使得在垂直于衬底边缘表面的方向上测量的胶层的边缘厚度为胶的中心厚度的至少105％ 层在垂直于衬底中心表面的方向上测量。 在一些实施例中，在垂直于衬底边缘处的表面的方向上测量的所述胶层的边缘厚度在胶层的中心厚度的约105％至150％的范围内，其测量方向是垂直于 在基板的中心处的表面，例如在垂直于基板中心的表面的方向上测量的胶层的中心厚度的约110％至120％的范围内。

公开(公告)号：US5804502A

公开(公告)日：1998-09-08

申请号：US786366

申请日：1997-01-16

申请人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

发明人： Calvin T. Gabriel ,  Dipankar Pramanik ,  Xi-Wei Lin

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L2924/0002

摘要： A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate. In some embodiments, the edge thickness of said glue layer measured in the direction normal to the surface at the edge of the substrate is in the range of approximately 105% to 150% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate, as for example in the range of approximately 110% to 120% of the center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

公开(公告)号：US08701054B2

公开(公告)日：2014-04-15

申请号：US13237818

申请日：2011-09-20

申请人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

发明人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L21/266 ,  H01L27/0207 ,  H01L29/1033 ,  H01L29/41758

摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

摘要翻译： 粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于 相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。 本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

公开(公告)号：US07681164B2

公开(公告)日：2010-03-16

申请号：US11848524

申请日：2007-08-31

申请人： Xi-Wei Lin ,  Victor Moroz

发明人： Xi-Wei Lin ,  Victor Moroz

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.

摘要翻译： 提出了一种将集成电路（IC）器件放置在IC芯片布局内的系统。 在操作期间，系统接收要放置在IC芯片布局内的IC器件，其中IC芯片布局包括一个或多个连续的扩散行。 接下来，系统将IC器件放置在连续的扩散行内。 然后，系统确定IC器件是否与其他IC器件电隔离。 如果是这样，系统将一个或多个隔离装置插入连续的扩散行内，使得IC器件可以与其它IC器件电隔离。 然后，该系统偏置一个或多个隔离装置，使得IC器件与连续的扩散排中的其它IC器件电隔离。

公开(公告)号：US20140167174A1

公开(公告)日：2014-06-19

申请号：US13717532

申请日：2012-12-17

申请人： Munkang Choi ,  Victor Moroz ,  Xi-Wei Lin

发明人： Munkang Choi ,  Victor Moroz ,  Xi-Wei Lin

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L21/02365 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor.

摘要翻译： 粗略地描述，集成电路晶体管结构具有半导体材料体，该主体具有两个纵向间隔开的掺杂源极/漏极体积，其间具有通道，位于主体外部并面向主体的至少一个表面的栅极堆叠 这个频道。 主体在通道容积内纵向地包含调节体积，并且在第一表面之后隔开第一距离并且与源/排出体积纵向隔开。 调节体积包括至少在晶体管处于截止状态时在每个纵向位置处具有不同于相同主体材料在同一纵向位置的电导率的调节体积材料。 在一个实施例中，调节体积材料是电介质。 在另一个实施例中，调节体积材料是电导体。

公开(公告)号：US20120011479A1

公开(公告)日：2012-01-12

申请号：US13237818

申请日：2011-09-20

申请人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

发明人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L21/266 ,  H01L27/0207 ,  H01L29/1033 ,  H01L29/41758

摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

摘要翻译： 粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于 相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。 本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

公开(公告)号：US07926018B2

公开(公告)日：2011-04-12

申请号：US11860775

申请日：2007-09-25

申请人： Victor Moroz ,  Xi-Wei Lin ,  Mark Rubin

发明人： Victor Moroz ,  Xi-Wei Lin ,  Mark Rubin

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068

摘要： A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.

摘要翻译： 提出了一种产生晶体管布局的系统。 在操作期间，系统接收晶体管库，其包括与晶体管栅极形状相关的制造晶体管的工作特性。 该系统还接收晶体管的一个或多个期望的工作特性。 接下来，系统基于晶体管库确定用于晶体管的晶体管栅极形状，使得具有晶体管栅极形状的制造晶体管基本上实现一个或多个期望的工作特性。 然后，系统产生包括晶体管栅极形状的晶体管的布局。

公开(公告)号：US20100187609A1

公开(公告)日：2010-07-29

申请号：US12390338

申请日：2009-02-20

申请人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

发明人： Victor Moroz ,  Munkang Choi ,  Xi-Wei Lin

IPC分类号： H01L27/088 ,  G06F17/50 ,  G03F1/00

CPC分类号： G06F17/5072 ,  H01L21/266 ,  H01L27/0207 ,  H01L29/1033 ,  H01L29/41758

摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

摘要翻译： 粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于 相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。 本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

公开(公告)号：US20090064072A1

公开(公告)日：2009-03-05

申请号：US11848524

申请日：2007-08-31

申请人： Xi-Wei Lin ,  Victor Moroz

发明人： Xi-Wei Lin ,  Victor Moroz

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.

摘要翻译： 提出了一种将集成电路（IC）器件放置在IC芯片布局内的系统。 在操作期间，系统接收要放置在IC芯片布局内的IC器件，其中IC芯片布局包括一个或多个连续的扩散行。 接下来，系统将IC器件放置在连续的扩散行内。 然后，系统确定IC器件是否与其他IC器件电隔离。 如果是这样，系统将一个或多个隔离装置插入连续的扩散行内，使得IC器件可以与其它IC器件电隔离。 然后，该系统偏置一个或多个隔离装置，使得IC器件与连续的扩散排中的其它IC器件电隔离。

公开(公告)号：US20090083688A1

公开(公告)日：2009-03-26

申请号：US11860775

申请日：2007-09-25

申请人： Victor Moroz ,  Xi-Wei Lin ,  Mark Rubin

发明人： Victor Moroz ,  Xi-Wei Lin ,  Mark Rubin

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.

摘要翻译： 提出了一种产生晶体管布局的系统。 在操作期间，系统接收晶体管库，其包括与晶体管栅极形状相关的制造晶体管的工作特性。 该系统还接收晶体管的一个或多个期望的工作特性。 接下来，系统基于晶体管库确定用于晶体管的晶体管栅极形状，使得具有晶体管栅极形状的制造晶体管基本上实现一个或多个期望的工作特性。 然后，系统产生包括晶体管栅极形状的晶体管的布局。