公开(公告)号：US5307476A

公开(公告)日：1994-04-26

申请号：US999470

申请日：1992-12-29

申请人： Timothy K. Waldrop ,  Paul R. Culley

发明人： Timothy K. Waldrop ,  Paul R. Culley

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F3/0601 ,  G06F13/28 ,  G06F5/06 ,  G06F2003/0692

摘要： The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.

摘要翻译： 本发明包括一种装置的两个变体，该装置产生提供给软盘控制器的读选通输入的IORC *总线信号的版本，该软盘控制器在软盘控制器和DMA之间的验证周期期间在适当的时间被断言 控制器。 这些设计允许82077软盘控制器在与不需要生成此信号的软件一起使用时，以FIFO模式正常运行。 这些设计包括使用PAL和某些总线信号输入来产生在验证传输期间在适当时间被断言的信号。 该信号与常规IORC *总线信号组合，以产生提供给软盘控制器的读选通输入的信号。

公开(公告)号：US5214767A

公开(公告)日：1993-05-25

申请号：US307773

申请日：1989-02-07

申请人： Christopher C. Wanner ,  Alan L. Goodrum ,  Paul R. Culley

发明人： Christopher C. Wanner ,  Alan L. Goodrum ,  Paul R. Culley

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F12/0835

摘要： A computer system which includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

公开(公告)号：US5168568A

公开(公告)日：1992-12-01

申请号：US307359

申请日：1989-02-06

申请人： John S. Thayer ,  Paul R. Culley ,  Montgomery C. McGraw

发明人： John S. Thayer ,  Paul R. Culley ,  Montgomery C. McGraw

IPC分类号： G06F13/36 ,  G06F13/374

CPC分类号： G06F13/36 ,  G06F13/374

摘要： A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems in which each processing module has a local cache. Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibited by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

公开(公告)号：US5163143A

公开(公告)日：1992-11-10

申请号：US431742

申请日：1990-11-03

申请人： Paul R. Culley ,  Mark Taylor

发明人： Paul R. Culley ,  Mark Taylor

IPC分类号： G06F12/08 ,  G06F13/36

CPC分类号： G06F12/0888 ,  G06F13/36

摘要： An enhanced processor lock cycle management system for computer systems including a processor 10 and a cache memory controller 12 which accommodates existing methodologies and provides an enhanced mode wherein processor lock cycles are not passed to the controlled 12 but control of the system bus 14 by controller 12 is maintained by inhibiting hold requests to the controller 12 by other system elements.

摘要翻译： 一种用于计算机系统的增强的处理器锁周期管理系统，包括处理器10和高速缓存存储器控制器12，其容纳现有方法并提供增强模式，其中处理器锁定周期不被传递到控制12，而是由控制器12控制系统总线14 通过由其他系统元件禁止对控制器12的保持请求来维护。

公开(公告)号：US5125088A

公开(公告)日：1992-06-23

申请号：US672748

申请日：1991-03-21

申请人： Paul R. Culley

发明人： Paul R. Culley

IPC分类号： G06F13/42

CPC分类号： G06F13/4243

摘要： A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors. A logic means permits a computer operator to select a speed which the operator wants the microprocessor to "simulate" and also permits the operator to select a type of older microprocessor which the operator wants the new high speed microprocessor to "simulate." A means of automatically varying the apparent microprocessor speed is also disclosed when data transfer from a floppy diskette are detected.

摘要翻译： 公开了一种具有高速微处理器的个人计算机，其以各种可选择的速度模式执行以提供与为较慢速度微处理器编写的应用程序的更大兼容性。 响应于不改变微处理器振荡器（时钟）的速度的速度选择信号来包括逻辑装置，而是改变微处理器的等待状态或“停止”状态的长度。 在STOP状态下，微处理器（CPU）在定时器超时之前不会运行总线周期，从而释放CPU STOP。 通过改变单触发定时器的时间延迟的长度，微处理器模拟微处理器速度变化，其具有具有较旧的微处理器的早期一代计算机的外观。 逻辑手段允许计算机操作员选择操作者希望微处理器“模拟”的速度，并且还允许操作者选择操作者希望新的高速微处理器“模拟”的一种较旧的微处理器。 当检测到来自软盘的数据传送时，还公开了自动改变表观微处理器速度的手段。

公开(公告)号：US5095428A

公开(公告)日：1992-03-10

申请号：US293221

申请日：1989-01-04

申请人： Karl N. Walker ,  Paul R. Culley

发明人： Karl N. Walker ,  Paul R. Culley

IPC分类号： G06F12/08

CPC分类号： G06F12/0835

摘要： A computer system which flushes the cache controller when a circuit board is being configured or is responding to an input/output write operation. The flush operation can be disabled for each circuit board location. A cache flush operation can also be directly requested.

公开(公告)号：US4787032A

公开(公告)日：1988-11-22

申请号：US905075

申请日：1986-09-08

申请人： Paul R. Culley

发明人： Paul R. Culley

IPC分类号： G06F1/08 ,  G06F1/24 ,  G06F13/28 ,  G06F9/46

CPC分类号： G06F1/08 ,  G06F1/24 ,  G06F13/285

摘要： A personal computer is disclosed having a microprocessor RESET/HOLD arbitration circuit and logic. The RESET/HOLD arbitration circuit requires a RESET signal to wait until any pending microprocessor "HOLD" is serviced or in the alternative and in the event the "RESET" signal is being processed causes the microprocessor "HOLD" signal to wait. The priority arbitration circuit and logic is essential to the proper operation of the 80386 microprocessor particularly in shifting from the "protected" mode of the microprocessor to the "real" mode of the microprocessor, since many third party application programs require the use of the microprocessor "protected" mode and require that the microprocessor be "reset" before returning to the "real" mode. The microprocessor "reset" must be accomplished by resetting the microprocessor without resetting the entire machine and without losing a HOLD request during the RESET. The computer system must also be capable of retaining a RESET request while either a DMA or REFRESH cycle is processed.

摘要翻译： 公开了一种具有微处理器RESET / HOLD仲裁电路和逻辑的个人计算机。 RESET / HOLD仲裁电路需要RESET信号才能等待直到任何待处理的微处理器“HOLD”被维护，或者在替代方案中，并且在“RESET”信号被处理的情况下，微处理器“HOLD”信号等待。 优先仲裁电路和逻辑对于80386微处理器的正确操作至关重要，特别是从微处理器的“保护”模式转移到微处理器的“真实”模式，因为许多第三方应用程序需要使用微处理器 “保护”模式，并要求微处理器在返回到“真实”模式之前“复位”。 微处理器“复位”必须通过复位微处理器而不必复位整个机器，而在复位期间不会丢失保持请求。 在处理DMA或REFRESH循环时，计算机系统还必须能够保留RESET请求。

公开(公告)号：US08205016B2

公开(公告)日：2012-06-19

申请号：US13046339

申请日：2011-03-11

申请人： Kevin B. Leigh ,  Paul R. Culley ,  Kevin G. Depew ,  Andrew Brown ,  Daniel N. Cripe ,  Jeffrey R. Hilland

发明人： Kevin B. Leigh ,  Paul R. Culley ,  Kevin G. Depew ,  Andrew Brown ,  Daniel N. Cripe ,  Jeffrey R. Hilland

IPC分类号： G06F3/00

CPC分类号： G06F9/4411

摘要： In at least some embodiments, a system comprises a plurality of electrical devices and management logic coupled to the electrical devices. While the electrical devices are each in a pre-boot environment, the management logic obtains information from the electrical devices and uses the information to determine electrical compatibility of, and/or configure, the electrical devices.

摘要翻译： 在至少一些实施例中，系统包括耦合到电气设备的多个电气设备和管理逻辑。 虽然电气设备都处于预引导环境中，但是管理逻辑从电气设备获得信息并且使用该信息来确定电气设备的电气兼容性和/或配置电气设备。

公开(公告)号：US07930440B2

公开(公告)日：2011-04-19

申请号：US11669912

申请日：2007-01-31

申请人： Kevin B. Leigh ,  Paul R. Culley ,  Kevin G. Depew ,  Andrew Brown ,  Daniel N. Cripe ,  Jeffrey R. Hilland

发明人： Kevin B. Leigh ,  Paul R. Culley ,  Kevin G. Depew ,  Andrew Brown ,  Daniel N. Cripe ,  Jeffrey R. Hilland

IPC分类号： G06F3/00

CPC分类号： G06F9/4411

摘要： In at least some embodiments, a system comprises a plurality of electrical devices and management logic coupled to the electrical devices. While the electrical devices are each in a pre-boot environment, the management logic obtains information from the electrical devices and uses the information to determine electrical compatibility of, and/or configure, the electrical devices.

摘要翻译： 在至少一些实施例中，系统包括耦合到电气设备的多个电气设备和管理逻辑。 虽然电气设备都处于预引导环境中，但是管理逻辑从电气设备获得信息并且使用该信息来确定电气设备的电气兼容性和/或配置电气设备。

公开(公告)号：US07565504B2

公开(公告)日：2009-07-21

申请号：US10401234

申请日：2003-03-27

申请人： David J. Garcia ,  Jeffrey R. Hilland ,  Paul R. Culley

发明人： David J. Garcia ,  Jeffrey R. Hilland ,  Paul R. Culley

IPC分类号： G06F12/00

CPC分类号： G06F12/145 ,  G06F12/1458

摘要： The disclosed embodiments may relate to memory window access, which may include a memory window and protection domain associated with a process. The memory window access setting or bit may also allow a plurality of memory windows to be associated with a protection domain for a process. The memory window access setting or bit may allow access to the memory window to be for the queue pairs in a certain protection domain or a designated queue pair.

摘要翻译： 所公开的实施例可以涉及存储器窗口访问，其可以包括与进程相关联的存储器窗口和保护域。 存储器窗口访问设置或位还可以允许多个存储器窗口与进程的保护域相关联。 存储器窗口访问设置或位可以允许访问存储器窗口以用于特定保护域或指定队列对中的队列对。