公开(公告)号：US5168568A

公开(公告)日：1992-12-01

申请号：US307359

申请日：1989-02-06

申请人： John S. Thayer ,  Paul R. Culley ,  Montgomery C. McGraw

发明人： John S. Thayer ,  Paul R. Culley ,  Montgomery C. McGraw

IPC分类号： G06F13/36 ,  G06F13/374

CPC分类号： G06F13/36 ,  G06F13/374

摘要： A bus arbitration protocol and accompanying bus arbitration logic for multiple-processor computer systems in which each processing module has a local cache. Several bus arbitration policies are enforced on contending devices which effectively introduce delay states into the arbitration behavior exhibited by each device. The bus arbitration protocol employs a distributed method of arbitration control involving an essentially fixed prioritization of arbitrating devices.

公开(公告)号：US5381530A

公开(公告)日：1995-01-10

申请号：US84632

申请日：1993-06-30

申请人： John S. Thayer ,  Montgomery C. McGraw

发明人： John S. Thayer ,  Montgomery C. McGraw

IPC分类号： G06F3/023 ,  G06F9/30 ,  G06F9/318 ,  G06F9/355 ,  G06F1/24

CPC分类号： G06F9/30189 ,  G06F9/30145

摘要： A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined criteria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

摘要翻译： 系统利用一个或多个可编程逻辑阵列或门阵列来调节微处理器可用的命令，并根据预定标准拦截某些命令。 系统选择并处理与INCE 80286或80386微处理器功能连接的键盘控制器的与FORCE-A20信号和CPU-RESET信号有关的指定命令。 该系统包括一个或多个可编程逻辑阵列或门阵列，用于允许所有输入命令直接通过键盘控制器，除了与FORCE-A20信号或CPU-RESET信号相关的命令序列。

公开(公告)号：US5226122A

公开(公告)日：1993-07-06

申请号：US88093

申请日：1987-08-21

申请人： John S. Thayer ,  Montgomery C. McGraw

发明人： John S. Thayer ,  Montgomery C. McGraw

IPC分类号： G06F3/023 ,  G06F9/30 ,  G06F9/318 ,  G06F9/355

CPC分类号： G06F9/30189 ,  G06F9/30145

摘要： A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined citeria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

摘要翻译： 系统利用一个或多个可编程逻辑阵列或门阵列来调节微处理器可用的命令，并根据预定的标准拦截某些命令。 系统选择并处理与INCE 80286或80386微处理器功能连接的键盘控制器的与FORCE-A20信号和CPU-RESET信号有关的指定命令。 该系统包括一个或多个可编程逻辑阵列或门阵列，用于允许所有输入命令直接通过键盘控制器，除了与FORCE-A20信号或CPU-RESET信号相关的命令序列。

公开(公告)号：US5341494A

公开(公告)日：1994-08-23

申请号：US165514

申请日：1993-12-10

申请人： John S. Thayer ,  Dale J. Mayer ,  Javier F. Izquierdo ,  Paul R. Culley ,  John A. Landry

发明人： John S. Thayer ,  Dale J. Mayer ,  Javier F. Izquierdo ,  Paul R. Culley ,  John A. Landry

IPC分类号： G06F12/06

CPC分类号： G06F12/0653

摘要： A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

摘要翻译： 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块中的任何位置定义逻辑128K字节的存储器块。 RAM由定义128千字节块的系统地址线寻址，输出数据为特定存储器模块提供行地址选通使能信号，以及将128K字节块放置在模块内所需的地址值。 各种其他参数，如写保护状态和存储器位置也由RAM提供。 提供了用于编程和读取RAM的电路和技术。

公开(公告)号：US5812876A

公开(公告)日：1998-09-22

申请号：US780019

申请日：1996-12-20

申请人： Mark W. Welker ,  John S. Thayer

发明人： Mark W. Welker ,  John S. Thayer

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F15/02

CPC分类号： G06F13/28 ,  G06F13/4013 ,  G06F13/4036

摘要： A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

摘要翻译： 一种计算机系统，其包括本地I / O单元上的DMA控制器，可由主机处理器或本地处理器进行编程。 提供信号标志和锁定位以允许确定本地DMA控制器的控制和传递信息。 另外，提供数据对准和填充电路。 电路被通知主处理器或其他设备所期望或利用的逻辑数据布置，并且知道本地处理器的数据排列。 电路根据传输方向和数据排列顺序获取和重新排列数据。 当重新对准使得填充是必要的时，电路进一步适当地对数据进行填补。

公开(公告)号：US5218686A

公开(公告)日：1993-06-08

申请号：US431656

申请日：1989-11-03

申请人： John S. Thayer

发明人： John S. Thayer

IPC分类号： G06F13/42

CPC分类号： G06F13/4234

摘要： A memory controller has an asynchronous portion and a synchronous portion. The synchronous portion is used when the system processor is accessing the memory, while the asynchronous portion is used when control of the memories is held by a DMA controller or a bus master located on a standardized bus.

公开(公告)号：US6009505A

公开(公告)日：1999-12-28

申请号：US759046

申请日：1996-12-02

申请人： John S. Thayer ,  Gary W. Thome ,  Brian E. Longhenry ,  John G. Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  Gary W. Thome ,  Brian E. Longhenry ,  John G. Favor ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F17/16

CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3877

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。 在一个实施例中，多个ALU可以从固定的源寄存器时隙位置接收一个操作数，其中固定时隙位置对于每个ALU可以是不同的。 操作数路由可以从任何源寄存器时隙位置提供另一个操作数，用于另一个输入到每个相应的ALU。

公开(公告)号：US5909572A

公开(公告)日：1999-06-01

申请号：US759025

申请日：1996-12-02

申请人： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

发明人： John S. Thayer ,  John G. Favor ,  Frederick D. Weber

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30072 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/3885 ,  G06F9/3887

摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

摘要翻译： 提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。 通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。 在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地路由和组合在矢量ALU。 向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。

公开(公告)号：US5598579A

公开(公告)日：1997-01-28

申请号：US234847

申请日：1994-04-25

申请人： Mark W. Welker ,  John S. Thayer

发明人： Mark W. Welker ,  John S. Thayer

IPC分类号： G06F13/28 ,  G06F13/40 ,  G06F15/02

CPC分类号： G06F13/28 ,  G06F13/4013 ,  G06F13/4036

摘要： A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.

摘要翻译： 一种计算机系统，其包括本地I / O单元上的DMA控制器，可由主机处理器或本地处理器进行编程。 提供信号标志和锁定位以允许确定本地DMA控制器的控制和传递信息。 另外，提供数据对准和填充电路。 电路被通知主处理器或其他设备所期望或利用的逻辑数据布置，并且知道本地处理器的数据排列。 电路根据传输方向和数据排列顺序获取和重新排列数据。 当重新对准使得填充是必要的时，电路进一步适当地对数据进行填补。

公开(公告)号：US06215504B1

公开(公告)日：2001-04-10

申请号：US08905685

申请日：1997-08-01

申请人： Brian E. Longhenry ,  Gary W. Thome ,  John S. Thayer

发明人： Brian E. Longhenry ,  Gary W. Thome ,  John S. Thayer

IPC分类号： G06T1120

CPC分类号： G06T3/40

摘要： A routable operand and selectable operation processor multimedia extension unit is employed to draw lines in a video system using an efficient, parallel technique. A first series of integral y pixel values and error values are calculated according to Bresenham's line drawing algorithm. Then, subsequent pixels and error values are calculated in parallel based on the previously calculated values.

摘要翻译： 使用可路由操作数和可选择的操作处理器多媒体扩展单元来使用有效的并行技术在视频系统中绘制线。 根据Bresenham的线图算法计算第一系列积分y像素值和误差值。 然后，基于先前计算的值并行计算后续像素和误差值。