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69 条记录 (耗时 0.04 秒)

    Programmable interrupt controller
    2.
    发明授权
    Programmable interrupt controller 失效
    可编程中断控制器

    公开(公告)号：US5101497A

    公开(公告)日：1992-03-31

    申请号：US691169

    申请日：1991-04-24

    申请人： Paul R. Culley ,  Montgomery McGraw ,  Karl N. Walker ,  Lazaro D. Perez

    发明人： Paul R. Culley ,  Montgomery McGraw ,  Karl N. Walker ,  Lazaro D. Perez

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： A computer system including a programmable interrupt controller wherein individual interrupt levels can be programmed to receive edge or level sensed interrupt signals. The controller includes a programmable register for storing the interrupt level designations for each interrupt level and associated interrupt recognition logic.

    摘要翻译： 一种包括可编程中断控制器的计算机系统，其中各个中断级别可被编程以接收边缘或电平感测的中断信号。 控制器包括一个可编程寄存器，用于存储每个中断级别和相关中断识别逻辑的中断级别标识。

    Method and apparatus for diagnosing fault states in a computer system
    6.
    发明授权
    Method and apparatus for diagnosing fault states in a computer system 失效
    用于诊断计算机系统中的故障状态的方法和装置

    公开(公告)号：US6000040A

    公开(公告)日：1999-12-07

    申请号：US739687

    申请日：1996-10-29

    申请人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

    发明人： Paul R. Culley ,  Joseph P. Miller ,  Daniel S. Hull ,  Siamak Tavallaei

    IPC分类号： G06F11/22 ,  G06F11/07 ,  G06F11/00

    CPC分类号： G06F11/0745 ,  G06F11/0748 ,  G06F11/079

    摘要： Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

    摘要翻译： 具有电路的计算机系统中的故障由连接的故障检测器来管理，以检测各个电路的故障状态。 故障管理器将故障状态与相应的电路相关联。 故障管理器包括连接到系统管理器以识别哪些电路在计算机系统中导致故障的操作。 与相应电路相关联的故障检测器被配置为检测各个电路的故障操作并产生故障状态信息。 连接中央管理器，从故障检测器累积故障状态信息。 其中一个电路包括总线，故障状态包括总线错误状况。 总线连接到多个设备，故障管理器识别多个设备中的哪一个引起总线错误状况。 其中一个电路包括多个模块，故障管理器识别多个模块的故障状态。 模块包括状态机。 其中一个电路包括内部时钟，并且电路的故障状态包括内部时钟不能正常工作。 其中一个电路包括温度传感器，并且电路的故障状态包括由温度传感器检测的高温条件。

    Double buffering operations between the memory bus and the expansion bus of a computer system
    8.
    发明授权
    Double buffering operations between the memory bus and the expansion bus of a computer system 失效

    公开(公告)号：US5870568A

    公开(公告)日：1999-02-09

    申请号：US903949

    申请日：1997-07-31

    申请人： Paul R. Culley ,  Mark Taylor

    发明人： Paul R. Culley ,  Mark Taylor

    IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F13/40 ,  G06F13/20

    CPC分类号： G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

    摘要： Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

    Interrupt handling in an asymmetric multiprocessor computer system
    9.
    发明授权
    Interrupt handling in an asymmetric multiprocessor computer system 失效
    非对称多处理器计算机系统中的中断处理

    公开(公告)号：US5247685A

    公开(公告)日：1993-09-21

    申请号：US996526

    申请日：1992-12-23

    申请人： John A. Landry ,  Paul R. Culley

    发明人： John A. Landry ,  Paul R. Culley

    IPC分类号： G06F13/26

    CPC分类号： G06F13/26

    摘要： Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

    摘要翻译： 两个独立运行的微处理器共享共同的控制，数据和地址总线。 当总线上的第一个微处理器在总线上被分配时，通过在下一个总线周期开始时将中断向量放置在总线上来响应所有可屏蔽的中断。 当第二个微处理器在总线上并且接收到可屏蔽中断时，禁止下一个总线周期的开始，使中断向量放在总线上。

    Computer system with high speed data transfer capabilities
    10.
    发明授权
    Computer system with high speed data transfer capabilities 失效
    具有高速数据传输能力的计算机系统

    公开(公告)号：US5159679A

    公开(公告)日：1992-10-27

    申请号：US378579

    申请日：1989-07-10

    申请人： Paul R. Culley

    发明人： Paul R. Culley

    IPC分类号： G06F13/28 ,  G06F13/42

    CPC分类号： G06F13/4243 ,  G06F13/28

    摘要： The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Thirty-two bit master units can downshift or step down to 16 bit operation to respond to 16 bit burstable responding units.