公开(公告)号：US08759871B2

公开(公告)日：2014-06-24

申请号：US13176780

申请日：2011-07-06

申请人： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

发明人： Ming-Hsiang Song ,  Jam-Wem Lee ,  Tzu-Heng Chang ,  Yu-Ying Hsu

IPC分类号： H01L29/66

CPC分类号： H01L27/0262

摘要： An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

摘要翻译： ESD保护电路包括IC的焊盘，耦合到用于缓冲数据的焊盘的电路，IC上的RC功率钳，以及第一和第二可硅可控整流器（SCR）电路。 RC电源钳位在正电源端子和接地端子之间。 第一SCR电路耦合在焊盘和正电源端子之间。 第一SCR电路具有耦合到RC功率钳位电路的第一触发输入。 第二SCR电路耦合在焊盘和接地端子之间。 第二SCR电路具有耦合到RC功率钳位电路的第二触发输入。 SCR电路中的至少一个包括栅极二极管，其被配置为选择性地在焊盘与正电源端子和接地端子之一之间提供短路或相对导电的电路径。

公开(公告)号：US08735993B2

公开(公告)日：2014-05-27

申请号：US13363026

申请日：2012-01-31

申请人： Ching-Hsiung Lo ,  Jam-Wem Lee ,  Wun-Jie Lin ,  Jen-Chou Tseng

发明人： Ching-Hsiung Lo ,  Jam-Wem Lee ,  Wun-Jie Lin ,  Jen-Chou Tseng

IPC分类号： H01L27/088

CPC分类号： H01L29/7831 ,  H01L27/0255 ,  H01L29/423 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

摘要： A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.

摘要翻译： 半导体器件可以包括用于ESD保护的finFET器件上的体接触。 半导体器件包括半导体鳍片，源极/漏极区域和主体接触。 源极/漏极区域和主体接触处于半导体鳍片中。 翅片的一部分横向在源极/漏极区域和身体接触之间。 半导体鳍片在衬底上。

公开(公告)号：US20140094009A1

公开(公告)日：2014-04-03

申请号：US14106100

申请日：2013-12-13

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Hung Cho Wang

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US07964893B2

公开(公告)日：2011-06-21

申请号：US12713599

申请日：2010-02-26

申请人： Jam-Wem Lee

发明人： Jam-Wem Lee

IPC分类号： H01L23/60

CPC分类号： H01L21/823431 ,  H01L27/0248 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT.

摘要翻译： 形成静电放电（ESD）器件的方法包括在衬底上形成彼此相邻的第一和第二半导体鳍; 在所述第一半导体鳍片和所述第二半导体鳍片上外延生长半导体材料，其中从所述第一半导体鳍片生长的所述半导体材料的第一部分接合从所述第二半导体鳍片生长的所述半导体材料的第二部分; 以及植入半导体材料的第一端和第二端以及第一和第二半导体鳍片的第一端部分别分别形成第一和第二植入区域。 在半导体材料的第一端和第二端之间形成P-N结。 P-N结是ESD二极管或NPN或PNP BJT中的结的结。

公开(公告)号：US20120126329A1

公开(公告)日：2012-05-24

申请号：US13362811

申请日：2012-01-31

申请人： Jam-Wem Lee

发明人： Jam-Wem Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/66628 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/785

摘要： Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate.

摘要翻译： 提供了仅顶部通道finFET器件。 本文所述的装置可以提供与finFET工艺流程兼容的本机装置。 可以在提供器件的沟道区域的翅片的顶部上形成栅极。 在一个实施例中，门仅设置在通道的一侧上，例如在翅片的顶部。 包括通道的翅片的侧壁可以邻接隔离结构。 在一个实施例中，在翅片之间形成隔离结构以提供用于形成栅极的平面。

公开(公告)号：US08153493B2

公开(公告)日：2012-04-10

申请号：US12267121

申请日：2008-11-07

申请人： Jam-Wem Lee

发明人： Jam-Wem Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/785

摘要： Provided is a top-channel only finFET device. The methods and devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate.

摘要翻译： 提供了仅顶部通道finFET器件。 本文所述的方法和装置可以提供与finFET工艺流程兼容的本机器件。 可以在提供器件的沟道区域的翅片的顶部上形成栅极。 在一个实施例中，门仅设置在通道的一侧上，例如在翅片的顶部。 包括通道的翅片的侧壁可以邻接隔离结构。 在一个实施例中，在翅片之间形成隔离结构以提供用于形成栅极的平面。

公开(公告)号：US20090315112A1

公开(公告)日：2009-12-24

申请号：US12143644

申请日：2008-06-20

申请人： Jam-Wem Lee

发明人： Jam-Wem Lee

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L21/823431 ,  H01L27/0248 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT.

摘要翻译： 形成静电放电（ESD）器件的方法包括在衬底上形成彼此相邻的第一和第二半导体鳍; 在所述第一半导体鳍片和所述第二半导体鳍片上外延生长半导体材料，其中从所述第一半导体鳍片生长的所述半导体材料的第一部分接合从所述第二半导体鳍片生长的所述半导体材料的第二部分; 以及植入半导体材料的第一端和第二端以及第一和第二半导体鳍片的第一端部分别分别形成第一和第二植入区域。 在半导体材料的第一端和第二端之间形成P-N结。 P-N结是ESD二极管或NPN或PNP BJT中的结的结。

公开(公告)号：US08963200B2

公开(公告)日：2015-02-24

申请号：US13527833

申请日：2012-06-20

申请人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

发明人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

IPC分类号： H01L29/45

CPC分类号： H01L27/0262 ,  H01L21/8248 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0921 ,  H01L29/0619 ,  H01L29/73 ,  H01L29/812

摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

摘要翻译： 提高保持电压SCR的方法和装置。 半导体器件包括第一导电类型的半导体衬底; 第一导电类型的第一井; 与第一阱相邻的第二导电类型的第二阱，形成p-n结的第一阱和第二阱的交点; 第一导电类型的第一扩散区域形成在第一阱处并且耦合到接地端子; 形成在第一阱处的第二导电类型的第一扩散区域; 第二导电类型的第二扩散区域形成在第二阱处并耦合到焊盘端子; 第二导电类型的第二扩散区形成在第二阱中; 以及与第二导电类型的第一扩散区相邻形成的与肖特基结相连的接地端子。 公开了用于形成装置的方法。

公开(公告)号：US08742491B2

公开(公告)日：2014-06-03

申请号：US13362811

申请日：2012-01-31

申请人： Jam-Wem Lee

发明人： Jam-Wem Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/66628 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/785

摘要： Provided is a top-channel only finFET device. The devices described herein may provide a native device that is compatible with a finFET process flow. A gate may be formed on the top of a fin providing the channel region of the device. In an embodiment, the gate is provided only on one side of the channel, for example, on the top of the fin. The sidewalls of the fin including channel may abut an isolation structure. In an embodiment, isolation structures are formed between the fins to provide a planar surface for the formation of a gate.

摘要翻译： 提供了仅顶部通道finFET器件。 本文所述的装置可以提供与finFET工艺流程兼容的本机装置。 可以在提供器件的沟道区域的翅片的顶部上形成栅极。 在一个实施例中，门仅设置在通道的一侧上，例如在翅片的顶部。 包括通道的翅片的侧壁可以邻接隔离结构。 在一个实施例中，在翅片之间形成隔离结构以提供用于形成栅极的平面。

公开(公告)号：US20130341676A1

公开(公告)日：2013-12-26

申请号：US13527833

申请日：2012-06-20

申请人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

发明人： Jam-Wem Lee ,  Tzu-Heng Chang ,  Tsung-Che Tsai ,  Ming-Hsiang Song

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L27/0262 ,  H01L21/8248 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0921 ,  H01L29/0619 ,  H01L29/73 ,  H01L29/812

摘要： Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.