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公开(公告)号：US09178008B2
公开(公告)日：2015-11-03
申请号：US13571441
申请日：2012-08-10
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译： 公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。 当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。
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公开(公告)号：US20130083436A1
公开(公告)日：2013-04-04
申请号：US13252396
申请日：2011-10-04
申请人： Jen-Chou TSENG , Tzu-Heng CHANG , Ming-Hsiang SONG
发明人： Jen-Chou TSENG , Tzu-Heng CHANG , Ming-Hsiang SONG
IPC分类号： H02H9/04 , H01L21/768
CPC分类号： H01L27/0292 , H01L21/822 , H01L23/481 , H01L23/60 , H01L27/0255 , H01L27/0262 , H01L27/0266 , H01L27/0285 , H01L2924/0002 , H01L2924/00
摘要： A chip includes a first circuit, a second circuit, a first interconnect, and a least one protection circuit. The first circuit has a first node, a first operational voltage node, and a first reference voltage node. The second circuit has a second node, a second operational voltage node, and a second reference voltage node. The first interconnect is configured to electrically connect the first node and the second node to form a 2.5D or a 3D integrated circuit. The at least one protection circuit is located at one or various locations of the chip.
摘要翻译： 芯片包括第一电路，第二电路，第一互连和至少一个保护电路。 第一电路具有第一节点，第一工作电压节点和第一参考电压节点。 第二电路具有第二节点，第二工作电压节点和第二参考电压节点。 第一互连被配置为电连接第一节点和第二节点以形成2.5D或3D集成电路。 至少一个保护电路位于芯片的一个或多个位置。
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公开(公告)号：US08324658B2
公开(公告)日：2012-12-04
申请号：US12759743
申请日：2010-04-14
申请人： Ming-Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh , Ming-Hsiang Song
发明人： Ming-Hsien Tsai , Chewn-Pu Jou , Fu-Lung Hsueh , Ming-Hsiang Song
IPC分类号： H01L29/73
CPC分类号： H01L29/73
摘要： An electrostatic discharge (ESD) protection circuit structure includes a dual directional silicon controlled rectifier (SCR) formed in a substrate. The SCR includes first and second P-wells laterally interposed by an N-well. A deep N-well is disposed underneath the P-wells and the N-well. First and second N-type regions are disposed in the first and second P-wells, respectively, and are coupled to a pair of pads. First and second P-type regions are disposed in the first and second P-wells, respectively, are coupled to the pads, and are disposed closer to the N-well than the first and second N-type regions, respectively.
摘要翻译： 静电放电（ESD）保护电路结构包括形成在衬底中的双向可控硅整流器（SCR）。 SCR包括由N阱横向插入的第一和第二P阱。 深井N井位于P井和N井的下面。 第一和第二N型区域分别设置在第一和第二P阱中，并且耦合到一对焊盘。 第一和第二P型区域分别设置在第一和第二P阱中，分别耦合到焊盘，并且分别设置成比第一和第二N型区域更靠近N阱。
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4.发明授权公开(公告)号：US08049250B2
公开(公告)日：2011-11-01
申请号：US12258946
申请日：2008-10-27
申请人： Ming-Hsiang Song , Jam-Wem Lee
发明人： Ming-Hsiang Song , Jam-Wem Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/7436 , H01L27/0262
摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.
摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。 在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。 公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。 这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。
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5.发明申请公开(公告)号：US20100103570A1
公开(公告)日：2010-04-29
申请号：US12258946
申请日：2008-10-27
申请人： Ming-Hsiang Song , Jam-Wem Lee
发明人： Ming-Hsiang Song , Jam-Wem Lee
CPC分类号： H01L29/7436 , H01L27/0262
摘要： Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.
摘要翻译： RC电源钳位电路和方法触发双SCR ESD保护。 在集成电路中，受保护的焊盘耦合到上部SCR电路和下部SCR电路; 并且两者耦合到耦合在正电压源和接地电压源之间的RC功率钳位电路。 公开了一种用于ESD保护的结构，其具有与第二导电类型的第二阱相邻的第一导电类型的第一阱，形成p-n结的边界以及电耦合到焊盘端子的每个阱中的焊盘接触扩散区; 在焊盘接触扩散区域附近提供附加的扩散，并且与焊接接触扩散区域电隔离，扩散区域和第一和第二阱形成两个SCR器件。 这些SCR器件在ESD事件期间被RC功率钳位电路注入到各个阱中的电流被触发。
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公开(公告)号：US20140042590A1
公开(公告)日：2014-02-13
申请号：US13571441
申请日：2012-08-10
IPC分类号： H01L29/92
摘要： Methods and apparatus are disclosed for manufacturing metal-insulator-metal (MIM) capacitors. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, which has a bottle neck. The MIM capacitors may comprise an electrode, which may be a top or bottom electrode, in contact with a sidewall of a via. The sidewall contact or the bottle neck of the electrode may burn out to form a high impedance path when the leakage current exceeds a specification, while the sidewall contact or the bottle neck of the electrode has no impact for normal MIM operations. The MIM capacitors may be used as decoupling capacitors.
摘要翻译： 公开了用于制造金属 - 绝缘体 - 金属（MIM）电容器的方法和装置。 MIM电容器可以包括电极，其可以是具有瓶颈的顶部或底部电极。 MIM电容器可以包括与通孔的侧壁接触的电极，其可以是顶部或底部电极。 当泄漏电流超过规格时，电极的侧壁接触或瓶颈可燃烧形成高阻抗路径，而电极的侧壁接触或瓶颈对于正常的MIM操作没有影响。 MIM电容器可用作去耦电容器。
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公开(公告)号：US20140027815A1
公开(公告)日：2014-01-30
申请号：US13558154
申请日：2012-07-25
申请人： Yu-Ti Su , Tzu-Heng Chang , Jen-Chou Tseng , Ming-Hsiang Song
发明人： Yu-Ti Su , Tzu-Heng Chang , Jen-Chou Tseng , Ming-Hsiang Song
IPC分类号： H01L27/06 , H01L21/8222
CPC分类号： H01L27/0817 , H01L27/0262 , H01L29/7436
摘要： Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.
摘要翻译： 快速开启可控硅整流器，实现ESD保护。 半导体器件包括第一导电类型的半导体衬底; 第二导电类型的第一阱; 第二导电类型的第二阱; 第一导电类型的第一扩散区域并耦合到第一端子; 第二导电类型的第一扩散区域; 第一导电类型的第二扩散区域; 第二导电类型的第二扩散区域; 其中第一导电类型的第一扩散区域和第二导电类型的第一扩散区域形成第一二极管，并且第一导电类型的第二扩散区域和第二导电类型的第二扩散区域形成第二二极管， 并且第一和第二二极管串联耦合在第一端子和第二端子之间。
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公开(公告)号：US20130009204A1
公开(公告)日：2013-01-10
申请号：US13176780
申请日：2011-07-06
申请人： Ming-Hsiang SONG , Jam-Wem LEE , Tzu-Heng CHANG , Yu-Ying HSU
发明人： Ming-Hsiang SONG , Jam-Wem LEE , Tzu-Heng CHANG , Yu-Ying HSU
IPC分类号： H01L27/06
CPC分类号： H01L27/0262
摘要： An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.
摘要翻译： ESD保护电路包括IC的焊盘，耦合到用于缓冲数据的焊盘的电路，IC上的RC功率钳，以及第一和第二可硅可控整流器（SCR）电路。 RC电源钳位在正电源端子和接地端子之间。 第一SCR电路耦合在焊盘和正电源端子之间。 第一SCR电路具有耦合到RC功率钳位电路的第一触发输入。 第二SCR电路耦合在焊盘和接地端子之间。 第二SCR电路具有耦合到RC功率钳位电路的第二触发输入。 SCR电路中的至少一个包括栅极二极管，其被配置为选择性地在焊盘与正电源端子和接地端子之一之间提供短路或相对导电的电路径。
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公开(公告)号：US09576949B2
公开(公告)日：2017-02-21
申请号：US13604299
申请日：2012-09-05
申请人： Jam-Wem Lee , Wan-Yen Lin , Ming-Hsiang Song , Cheng-Hsiung Kuo , Yue-Der Chih
发明人： Jam-Wem Lee , Wan-Yen Lin , Ming-Hsiang Song , Cheng-Hsiung Kuo , Yue-Der Chih
CPC分类号： H01L27/0727 , H01L27/0222 , H01L29/0619 , H01L29/872 , H02M3/07
摘要： A P-type Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) includes a gate, a first source/drain region connected to the gate, and a second source/drain region on an opposite side of the gate than the first source/drain region. A first Schottky diode includes a first anode connected to the first source/drain region, and a first cathode connected to a body of the PMOSFET. A second Schottky diode includes a second anode connected to the second source/drain region, and a second cathode connected to the body of the PMOSFET.
摘要翻译： P型金属氧化物半导体场效应晶体管（PMOSFET）包括栅极，连接到栅极的第一源极/漏极区域和栅极相对于第一源极/漏极的第二源极/漏极区域 地区。 第一肖特基二极管包括连接到第一源极/漏极区域的第一阳极和连接到PMOSFET主体的第一阴极。 第二肖特基二极管包括连接到第二源极/漏极区的第二阳极和连接到PMOSFET的主体的第二阴极。
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公开(公告)号：US08610220B2
公开(公告)日：2013-12-17
申请号：US13472890
申请日：2012-05-16
申请人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
发明人： Yue-Der Chih , Jam-Wem Lee , Cheng-Hsiung Kuo , Tsung-Che Tsai , Ming-Hsiang Song , Hung-Cheng Sung , Roger Wang
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L21/823481 , H01L21/823493 , H01L29/1083 , H01L29/36 , H01L29/423
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。
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