公开(公告)号：US20220336481A1

公开(公告)日：2022-10-20

申请号：US17857034

申请日：2022-07-03

Applicant: Winbond Electronics Corp.

Inventor： Hsin-Huang Shen ,  Yu-Shu Cheng ,  Yao-Ting Tsai

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/78

Abstract: A manufacturing method of semiconductor device is provided. In the manufacturing method, a tunneling dielectric layer, floating gates on the tunneling dielectric layer, an ONO layer on the floating gates, and control gates on the ONO layer are formed. During the formation of the floating gates and the control gates, reactive-ion etching (R.I.E.) is not used at all, and thus damage to the floating and control gates from high-density plasma is prevented, such as charge trap in the floating gates may be significantly reduced to improve the reliability of data storage.

公开(公告)号：US11424254B2

公开(公告)日：2022-08-23

申请号：US16713020

申请日：2019-12-13

Applicant: Winbond Electronics Corp.

Inventor： Hsin-Huang Shen ,  Yu-Shu Cheng ,  Yao-Ting Tsai

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/06 ,  H01L29/788 ,  H01L21/762 ,  H01L21/28 ,  H01L29/78 ,  H01L21/3213

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a plurality of floating gates, a tunneling dielectric layer, a plurality of control gates, and an ONO layer. The floating gates are located on the substrate, and the tunneling dielectric layer is located between the substrate and each of the floating gates. The control gates are located on the floating gates, and the ONO layer is located on two sidewalls of each of the control gates and between each of the control gates and each of the floating gates.

公开(公告)号：US10971508B2

公开(公告)日：2021-04-06

申请号：US16391326

申请日：2019-04-23

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang ,  Jung-Ho Chang ,  Hsiu-Han Liao

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3105 ,  H01L29/788 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/78

Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

公开(公告)号：US10147730B2

公开(公告)日：2018-12-04

申请号：US15922888

申请日：2018-03-15

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/115 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524 ,  H01L27/1157

Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.