公开(公告)号：US20200343256A1

公开(公告)日：2020-10-29

申请号：US16391326

申请日：2019-04-23

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang ,  Jung-Ho Chang ,  Hsiu-Han Liao

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/78 ,  H01L29/788

Abstract: Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

公开(公告)号：US20180204846A1

公开(公告)日：2018-07-19

申请号：US15922888

申请日：2018-03-15

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/11521 ,  H01L29/417

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.

公开(公告)号：US20180047737A1

公开(公告)日：2018-02-15

申请号：US15352594

申请日：2016-11-16

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L21/28 ,  H01L29/788 ,  H01L29/49

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.

公开(公告)号：US20240244838A1

公开(公告)日：2024-07-18

申请号：US18617590

申请日：2024-03-26

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H10B41/30 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US20220367496A1

公开(公告)日：2022-11-17

申请号：US17317872

申请日：2021-05-11

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao

IPC: H01L27/11526

Abstract: A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.

公开(公告)号：US20220037345A1

公开(公告)日：2022-02-03

申请号：US17376079

申请日：2021-07-14

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Hsiu-Han Liao ,  Che-Fu Chuang

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66

Abstract: Disposed are a semiconductor structure, a manufacturing method thereof and a flash memory. The semiconductor structure includes a substrate, first isolation structures, a gate structure and an oxide layer. The first isolation structures define a first active area in a peripheral region of the substrate. The oxide layer is disposed on the substrate in the first active area and covered by the first isolation structures. The oxide layer and the first isolation structures define an opening exposing the substrate. The gate structure is disposed on the substrate in the first active area and includes a gate dielectric layer disposed in the opening and a gate disposed on the gate dielectric layer. The oxide layer is located around the gate dielectric layer. The width of the bottom surface of the gate is less than that of the top surface of the first active area.

公开(公告)号：US09972631B2

公开(公告)日：2018-05-15

申请号：US15352594

申请日：2016-11-16

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao ,  Yao-Ting Tsai

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/41758 ,  H01L29/42328 ,  H01L29/4975 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.

公开(公告)号：US11974428B2

公开(公告)日：2024-04-30

申请号：US17564259

申请日：2021-12-29

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Yao-Ting Tsai ,  Hsiu-Han Liao

IPC: H10B41/30 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/66825 ,  H01L29/7883

Abstract: Provided are a memory device and a method of manufacturing the same. The memory device includes: a stack structure; a first source/drain region and a second source/drain region located in a substrate beside the stack structure; a first self-aligned contact connected to the first source/drain region; a second self-aligned contact connected to the second source/drain region; a first liner structure located between the first self-aligned contact and a first sidewall of the stack structure; and a second liner structure located between the second self-aligned contact and a second sidewall of the stack structure. The first liner structure and the second liner structure are not connected and do not cover the stack structure.

公开(公告)号：US20240021266A1

公开(公告)日：2024-01-18

申请号：US17866558

申请日：2022-07-18

Applicant: Winbond Electronics Corp.

Inventor： Yao-Ting Tsai ,  Che-Fu Chuang

IPC: G11C29/00 ,  G11C29/52

CPC classification number: G11C29/72 ,  G11C29/785 ,  G11C29/52

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

公开(公告)号：US11839076B2

公开(公告)日：2023-12-05

申请号：US17472912

申请日：2021-09-13

Applicant: Winbond Electronics Corp.

Inventor： Che-Fu Chuang ,  Hsiu-Han Liao

IPC: H10B41/47 ,  H10B41/46 ,  H10B41/44

CPC classification number: H10B41/47 ,  H10B41/46 ,  H10B41/44

Abstract: A method of forming a semiconductor structure includes forming first to third sacrificial layers on a substrate including a memory cell area and a peripheral area with a word line area. The second and third sacrificial layers in the word line area are removed to expose the top surface of the first sacrificial layer. The first sacrificial layer in the word line area and the third sacrificial layer in the memory cell area are removed. A word line dielectric layer and a first conductive layer are formed on the substrate in the word line area. The first and second sacrificial layers in the memory cell area are removed. A tunneling dielectric layer is formed on the substrate in the memory cell area. The thickness of the tunneling dielectric layer is smaller than the thickness of the word line dielectric layer.