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    Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling
    31.
    发明授权
    Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling 有权
    用于非易失性存储器的受控编程的显示位线耦合的装置

    公开(公告)号：US07206235B1

    公开(公告)日：2007-04-17

    申请号：US11251458

    申请日：2005-10-14

    申请人： Jeffrey W. Lutze ,  Yan Li ,  Siu L. Chan

    发明人： Jeffrey W. Lutze ,  Yan Li ,  Siu L. Chan

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

    摘要： The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

    摘要翻译： 解决位线对位线耦合在非易失性存储器中的影响。 在编程的存储元件的位线上施加禁止电压，以在编程电压的一部分期间禁止编程。 随后在编程电压期间去除抑制电压以允许编程发生。 由于位线的接近，位线电压的变化被耦合到相邻的未选位线，将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。 为了防止这种情况，在位线电压变化期间临时调整选择栅极电压，以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。

    Behavior based programming of non-volatile memory
    32.
    发明授权
    Behavior based programming of non-volatile memory 有权
    非易失性存储器的基于行为的编程

    公开(公告)号：US07177199B2

    公开(公告)日：2007-02-13

    申请号：US10689333

    申请日：2003-10-20

    申请人： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

    发明人： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

    摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

    摘要翻译： 通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。 例如，一组编程脉冲被施加到一组闪存单元的字线。 确定哪些存储器单元更容易编程，哪些存储器单元难以编程。 可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。 然后，编程过程将继续调整的位线电压（或其他参数）。

    PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE
    34.
    发明申请
    PROGRAMMING AND SELECTIVELY ERASING NON-VOLATILE STORAGE 有权
    编程和选择性擦除非易失性存储

    公开(公告)号：US20110261621A1

    公开(公告)日：2011-10-27

    申请号：US13168855

    申请日：2011-06-24

    申请人： Jeffrey W. Lutze ,  Yan Li

    发明人： Jeffrey W. Lutze ,  Yan Li

    IPC分类号： G11C16/16 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3418

    摘要： A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.

    摘要翻译： 非易失性存储系统对多个非易失性存储元件执行编程，并且有选择地执行应该保持擦除的非易失性存储元件的至少一个子集的重新擦除，而无需有意地擦除编程数据。

    Source side self boosting technique for non-volatile memory
    36.
    发明授权
    Source side self boosting technique for non-volatile memory 有权
    源极自增强技术用于非易失性存储器

    公开(公告)号：US06859397B2

    公开(公告)日：2005-02-22

    申请号：US10379608

    申请日：2003-03-05

    申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

    发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

    IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

    CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

    摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

    摘要翻译： 以避免程序干扰的方式编程非易失性半导体存储器系统（或其他类型的存储器系统）。 在包括使用NAND架构的闪存系统的一个实施例中，通过在编程处理期间增加NAND串的源侧的沟道电位来避免程序干扰。 一个示例性实施方案包括将电压（例如Vdd）施加到源极触点，并接通源极侧选择晶体管，用于对应于被抑制的电池的NAND触发。 另一种实施方案包括在施加编程电压之前，将预充电电压施加到对应于被禁止的单元的NAND串的未选择字线。

    Method for controlled programming of non-volatile memory exhibiting bit line coupling
    39.
    发明授权
    Method for controlled programming of non-volatile memory exhibiting bit line coupling 失效
    显示位线耦合的非易失性存储器的受控编程方法

    公开(公告)号：US07286406B2

    公开(公告)日：2007-10-23

    申请号：US11250735

    申请日：2005-10-14

    申请人： Jeffrey W. Lutze ,  Yan Li ,  Siu L. Chan

    发明人： Jeffrey W. Lutze ,  Yan Li ,  Siu L. Chan

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3418 ,  G11C16/3427

    摘要： The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

    摘要翻译： 解决位线对位线耦合在非易失性存储器中的影响。 在编程的存储元件的位线上施加禁止电压，以在编程电压的一部分期间禁止编程。 随后在编程电压期间去除抑制电压以允许编程发生。 由于位线的接近，位线电压的变化被耦合到相邻的未选位线，将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。 为了防止这种情况，在位线电压变化期间临时调整选择栅极电压，以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。

    Detecting over programmed memory
    40.
    发明授权
    Detecting over programmed memory 有权
    检测编程内存

    公开(公告)号：US07215575B2

    公开(公告)日：2007-05-08

    申请号：US11124709

    申请日：2005-05-09

    申请人： Jian Chen ,  Yan Li ,  Jeffrey W. Lutze

    发明人： Jian Chen ,  Yan Li ,  Jeffrey W. Lutze

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/3463 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

    摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

    摘要翻译： 在非易失性半导体存储器系统（或其他类型的存储器系统）中，通过改变该存储器单元的阈值电压对存储器单元进行编程。 由于系统中不同存储器单元的编程速度的变化，存在一些存储器单元将被过度编程的可能性。 也就是说，在一个示例中，阈值电压将被移动超过预期值或值的范围。 本发明包括确定存储器单元是否被过度编程。