公开(公告)号：US06975537B2

公开(公告)日：2005-12-13

申请号：US11049802

申请日：2005-02-03

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

公开(公告)号：US06859397B2

公开(公告)日：2005-02-22

申请号：US10379608

申请日：2003-03-05

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Masaaki Higashitani

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

摘要翻译： 以避免程序干扰的方式编程非易失性半导体存储器系统（或其他类型的存储器系统）。 在包括使用NAND架构的闪存系统的一个实施例中，通过在编程处理期间增加NAND串的源侧的沟道电位来避免程序干扰。 一个示例性实施方案包括将电压（例如Vdd）施加到源极触点，并接通源极侧选择晶体管，用于对应于被抑制的电池的NAND触发。 另一种实施方案包括在施加编程电压之前，将预充电电压施加到对应于被禁止的单元的NAND串的未选择字线。

公开(公告)号：US07616499B2

公开(公告)日：2009-11-10

申请号：US11617541

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.

摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。

公开(公告)号：US07633807B2

公开(公告)日：2009-12-15

申请号：US11624052

申请日：2007-01-17

申请人： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

发明人： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

摘要翻译： 通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。 例如，一组编程脉冲被施加到一组闪存单元的字线。 确定哪些存储器单元更容易编程，哪些存储器单元难以编程。 可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。 然后，编程过程将继续调整的位线电压（或其他参数）。

公开(公告)号：US07046555B2

公开(公告)日：2006-05-16

申请号：US10665685

申请日：2003-09-17

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

IPC分类号： G11C16/04

CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

摘要翻译： 用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。

公开(公告)号：US06914823B2

公开(公告)日：2005-07-05

申请号：US10628962

申请日：2003-07-29

申请人： Jian Chen ,  Yan Li ,  Jeffrey W. Lutze

发明人： Jian Chen ,  Yan Li ,  Jeffrey W. Lutze

IPC分类号： G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3404 ,  G11C16/3454

摘要： In a non-volatile semiconductor memory system (or other type of memory system), a memory cell is programmed by changing the threshold voltage of that memory cell. Because of variations in the programming speeds of different memory cells in the system, the possibility exists that some memory cells will be over programmed. That is, in one example, the threshold voltage will be moved past the intended value or range of values. The present invention includes determining whether the memory cells are over programmed.

公开(公告)号：US07652918B2

公开(公告)日：2010-01-26

申请号：US11617546

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.

摘要翻译： 一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。 管理电路与所述存储元件阵列通信并执行编程和读取操作。 编程操作包括编程多个多状态存储数据。 读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

公开(公告)号：US07414894B2

公开(公告)日：2008-08-19

申请号：US11389557

申请日：2006-03-23

申请人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

发明人： Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Kazunori Kanebako ,  Tomoharu Tanaka

IPC分类号： G11C11/34

CPC分类号： G11C16/3495 ,  G11C16/04 ,  G11C16/349 ,  G11C29/50 ,  G11C29/50004

摘要： A number of methods for identifying cells with poor subthreshold slope and reduced transconductance. A first set of techniques focuses on the poor subthreshold behavior of degraded storage elements by cycling cells and then programming them to a state above the ground state and the reading them with a control gate voltage below the threshold voltage of this state to see if they still conduct. A second set of embodiments focuses on weak transconductance behavior by reading programmed cells with a control gate voltage well above the threshold voltage. A third set of embodiments alters the voltage levels at the source-drain regions of the storage elements. The current-voltage curve of a good storage element is relatively stable under this shift in bias conditions, while degraded elements exhibit a larger shift. The amount of shift can be used to differentiate the good elements from the bad.

摘要翻译： 用于鉴定具有差的亚阈值斜率和降低的跨导的细胞的许多方法。 第一组技术集中在通过循环单元对劣化的存储元件的差的亚阈值行为进行编程，然后将它们编程到高于基态的状态，并以低于该状态的阈值电压的控制栅极电压读取它们，以查看它们是否仍然 进行。 第二组实施例通过利用远高于阈值电压的控制栅极电压读取编程单元来侧重于弱跨导行为。 第三组实施例改变存储元件的源极 - 漏极区域处的电压电平。 在偏置条件下的这种偏移下，良好存储元件的电流 - 电压曲线相对稳定，而退化元件表现出较大的偏移。 偏移量可以用来区分好的元素和坏的元素。

公开(公告)号：US20080158990A1

公开(公告)日：2008-07-03

申请号：US11617546

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： A memory system, comprising an array of storage elements divided into logical blocks and pages within said logical blocks and a managing circuit is provided. The managing circuit is in communication with said array of storage elements and performs programming and reading operations. The programming operations include programming a plurality of multi-state storage data. The reading operations include defining an retention margin between adjacent data thresholds, determining whether bits are present in a portion of the data retention margin, and if the number of bits in the portion of retention margin exceeds a threshold, generating an error.

摘要翻译： 一种存储器系统，包括分成逻辑块的存储元件阵列和所述逻辑块内的页面，并且提供管理电路。 管理电路与所述存储元件阵列通信并执行编程和读取操作。 编程操作包括编程多个多状态存储数据。 读取操作包括定义相邻数据阈值之间的保留余量，确定位是否存在于数据保留余量的一部分中，以及如果保留余量部分中的位数超过阈值，则产生错误。

公开(公告)号：US20080158989A1

公开(公告)日：2008-07-03

申请号：US11617541

申请日：2006-12-28

申请人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

发明人： Jun Wan ,  Jeffrey W. Lutze ,  Jian Chen ,  Yan Li ,  Alex Mak

IPC分类号： G11C16/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Data verification in a memory device using a portion of a data retention margin is provided. A bit count is read from the region to determine whether errors will result in the memory. A read in one or more retention margin portions is performed after the normal program verify sequence and if the number of bits in these regions is more than a pre-set the memory will fail verify status. A method of verifying data in a memory device includes the steps of: defining an retention margin between adjacent data thresholds; programming the memory device with data; determining whether bits are present in the data retention margin; and if the number of bits in the retention margin exceeds a threshold, generating an error.

摘要翻译： 提供了使用部分数据保留余量的存储器件中的数据验证。 从区域读取位计数，以确定错误是否会导致内存。 在正常程序验证序列之后执行在一个或多个保留边缘部分中的读取，并且如果这些区域中的位数大于预设，则存储器将失败验证状态。 验证存储器件中的数据的方法包括以下步骤：定义相邻数据阈值之间的保留余量; 使用数据对存储设备进行编程; 确定位是否存在于数据保留余量中; 并且如果保留余量中的比特数超过阈值，则产生错误。