公开(公告)号：US20220163937A1

公开(公告)日：2022-05-26

申请号：US17524384

申请日：2021-11-11

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Heng-Chia HSU ,  Chen-Yin LIN ,  Yu-Shu YEH ,  Chien-Chung WANG ,  Chin-Hung TAN

IPC: G05B19/042

Abstract: An integrated control management system includes an input output device. The input output device includes a database, a memory module, a first processing module, and a second processing module. The memory module receives and stores a plurality of integrated control commands, and one of the integrated control commands is generated based on a hardware control command for setting a hardware control transmitted by another input and output device. The first processing module reads the integrated control command from the memory module and obtains the hardware control data from the integrated control command. The first processing module updates the hardware control data to the database. The second processing module reads the database and updates the hardware control data stored in the database to another database in another input output device. The second processing module sets the hardware control based on the hardware control data stored in the database.

公开(公告)号：US20220147340A1

公开(公告)日：2022-05-12

申请号：US17453464

申请日：2021-11-03

Applicant: Mitac Computing Technology Corporation

Inventor： Chih-Peng CHANG

IPC: G06F8/65 ,  G06F9/445 ,  G06F13/42

Abstract: A method of updating firmware of a BMC of a server, the server includes the BMC and a PLD, the method includes: in response to receipt of a firmware update instruction to update the firmware of the BMC, the BMC storing in the PLD a firmware configuration file that contains current settings; the BMC updating the firmware after storing the firmware configuration file in the PLD; the BMC being reset after updating the firmware; and the BMC executing an initializing process that includes sub-steps of reading the firmware configuration file from the PLD and applying the current settings contained in the firmware configuration file to the firmware.

公开(公告)号：US11010317B2

公开(公告)日：2021-05-18

申请号：US16885431

申请日：2020-05-28

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Ming-Shou Shen

IPC: G06F3/00 ,  G06F13/20 ,  G06F11/14 ,  G06F13/12

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node and a second computer node. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; and (B) transmitting, by the first BMC and to the second BMC via electrical connection between the first and second BMCs, a reset signal that corresponds to the reset command, so as to trigger reset of the second BMC.

公开(公告)号：US20210004168A1

公开(公告)日：2021-01-07

申请号：US16898522

申请日：2020-06-11

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Tsung-Yin Lee ,  Jen-Chih Lee ,  Yi-Lan Lin

IPC: G06F3/06

Abstract: A method for managing HDD expanders in a cluster storage system is provided. The method according to one embodiment is implemented by each of the HDD expanders, and includes: indicating a device type of HDD expander to a parent node thereof when a device-type request originates from the parent node; and indicating a device type not of HDD expander to the parent node otherwise. The method according to another embodiment is implemented by each HDD expander connected indirectly to a root node, and includes: indicating a device type not of HDD expander to the root node when a device-type request originates from the root node; and indicating a device type of HDD expander to a node that initiates the device-type request otherwise.

公开(公告)号：US10860404B2

公开(公告)日：2020-12-08

申请号：US16260965

申请日：2019-01-29

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Yi-Hua Wu ,  I-Hsin Chen ,  Chung-Hsien Liu

IPC: G06F11/07

Abstract: This application provides a server and a debugging method therefor. The debugging method for a server includes receiving, by a complex programmable logic device (CPLD), a control signal generated by a switching member, and generating a switching signal; and switching, by a bus switch, a communication connection of a communications port to a debug port or a Serial Over LAN port of a baseboard management controller (BMC) based on the switching signal. In this way, debugging work is completed or industrial control application information is received at the communications port.

公开(公告)号：US10802918B2

公开(公告)日：2020-10-13

申请号：US16244639

申请日：2019-01-10

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Wei-Lung Shen ,  Chen-Nan Hsiao ,  Chih-Cheng Wang ,  Chung-Huang Liu

IPC: G06F3/06 ,  G06F11/14

Abstract: A computer device, a server device, and a method for controlling a hybrid memory unit thereof are provided. The control method includes: executing, by a processing unit, an operating system (OS) in a working mode of the computer device; triggering, by a soft off control signal or a soft reset control signal when the processing unit executes the OS, the processing unit to enter an interrupt processing mode; executing, by the processing unit, basic input/output system (BIOS) program code in the interrupt processing mode; and controlling, by the processing unit by using the BIOS program code, to store data from a volatile memory into a non-volatile memory corresponding to the volatile memory.

公开(公告)号：US10713193B2

公开(公告)日：2020-07-14

申请号：US16188458

申请日：2018-11-13

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Ming-Shou Shen

IPC: G06F3/00 ,  G06F13/20 ,  G06F11/14 ,  G06F13/12

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node, a second computer node and a control unit. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; (B) transmitting, by the first BMC and to the control unit, a control signal that corresponds to the reset command; and (C) transmitting, by the control unit and to the second BMC, a reset signal that corresponds to the control signal, so as to trigger reset of the second BMC.

公开(公告)号：US20200159541A1

公开(公告)日：2020-05-21

申请号：US16588174

申请日：2019-09-30

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Jyun-Hong LI ,  Chi-Hao KUAN

IPC: G06F9/4401 ,  G06K9/62 ,  G06K9/46 ,  G06N20/00

Abstract: A method for identifying a boot stage of a BIOS of a computer device is provided. A control terminal receives screen information data indicative of a current BIOS screen image of the computer device, acquires current screen information based on the screen information data, acquires feature vector based on the current screen information, uses an image classification model to classify the current information into a screen category, and generates boot stage information indicative of a boot stage corresponding to the screen category.

公开(公告)号：US20190286527A1

公开(公告)日：2019-09-19

申请号：US16244639

申请日：2019-01-10

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Wei-Lung SHEN ,  Chen-Nan HSIAO ,  Chih-Cheng WANG ,  Chung-Huang LIU

IPC: G06F11/14 ,  G06F3/06

Abstract: A computer device, a server device, and a method for controlling a hybrid memory unit thereof are provided. The control method includes: executing, by a processing unit, an operating system (OS) in a working mode of the computer device; triggering, by a soft off control signal or a soft reset control signal when the processing unit executes the OS, the processing unit to enter an interrupt processing mode; executing, by the processing unit, basic input/output system (BIOS) program code in the interrupt processing mode; and controlling, by the processing unit by using the BIOS program code, to store data from a volatile memory into a non-volatile memory corresponding to the volatile memory.

公开(公告)号：US10223229B2

公开(公告)日：2019-03-05

申请号：US15276184

申请日：2016-09-26

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wei Wang

IPC: H04L12/24 ,  G06F11/30 ,  G06F1/20 ,  G06F13/364 ,  G06F13/40

Abstract: A system includes a bus, multiple BMCs, and a control unit. Each BMC generates heartbeat signals and acquire operation data associated with a to-be-monitored unit once being initiated, and operates in one of a master mode and a slave mode according to a corresponding decision signal. One of the BMCs which operates in the master mode is configured to receive via the bus the operation data from the rest of the BMCs which operate(s) in the slave mode for monitoring the to-be-monitored unit. The control unit is configured to, according to the heartbeat signals, generate the corresponding decision signals for controlling a first normally operating one of the BMCs to operate in the master mode and the rest of the BMCs to operate in the slave mode.