公开(公告)号：US06957179B2

公开(公告)日：2005-10-18

申请号：US09982094

申请日：2001-10-18

Applicant: Anthony Debling

Inventor： Anthony Debling

IPC: G06F13/10 ,  G06F9/455

CPC classification number: G06F13/105

Abstract: There is disclosed a method of communicating with an integrated circuit chip having plural components thereon, the components including digital processing circuitry and an on-chip emulator connected to the digital processing circuitry for initiating command and control sequences for the digital processing circuitry in response to externally applied signals or in response to detected states of the digital processing circuitry. The method comprising of providing a universal serial bus having first and second ends, the first end being connected to the on-chip emulator; providing a computer device having a digital processor, a universal serial bus port connected to the second end of the universal serial bus, and a second port for connection to a communication channel; assigning at least one of the components with a respective address; sending a remote procedure call from the component over the universal serial bus to the computer device, the remote procedure call including data indicative of the address of the component; in response thereto, causing the computer device to generate a socket call over the communication channel thereby creating a first socket at the computer device and a second socket at a computer connected to the communication channel; in the computer device, receiving a response at the first socket; and sending information derived from the response over the universal serial bus to the component.

Abstract translation: 公开了一种与其上具有多个部件的集成电路芯片进行通信的方法，所述组件包括数字处理电路和连接到数字处理电路的片上仿真器，用于响应于外部来启动用于数字处理电路的命令和控制序列 应用信号或响应于数字处理电路的检测状态。 该方法包括提供具有第一和第二端的通用串行总线，第一端连接到片上仿真器; 提供具有数字处理器，连接到通用串行总线的第二端的通用串行总线端口和用于连接到通信信道的第二端口的计算机设备; 将至少一个组件分配给相应的地址; 通过所述通用串行总线将所述组件的远程过程调用发送到所述计算机设备，所述远程过程调用包括指示所述组件的地址的数据; 响应于此，使得计算机设备通过通信信道生成套接字呼叫，从而在计算机设备处创建第一插座，并在连接到通信信道的计算机上产生第二插座; 在所述计算机设备中，在所述第一套接字处接收响应; 并将通过通用串行总线的响应导出的信息发送到组件。

公开(公告)号：US20050229127A1

公开(公告)日：2005-10-13

申请号：US10816799

申请日：2004-04-02

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: The present invention is directed to methods for verifying adequate synchronisation of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to another therein. The method includes the steps of (i) modelling at least one of the functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal, (ii) simulating the circuit, and (iii) determining which functional element is a synchroniser to thereby identify if there is a synchronisation problem for a signal passing from one clock environment to another.

Abstract translation: 本发明涉及用于验证跨时钟环境的信号的充分同步的方法。 根据一个示例性方法，设计中的电路包括多个功能元件和多个时钟环境，并且具有从一个时钟环境到另一个时钟环境的一个或多个信号。 该方法包括以下步骤：（i）在时钟信号的定时事件，（ii）模拟电路之后的预定时间内将功能元件中的至少一个功能元件建模为具有未知状态作为输出，以及（iii）确定 哪个功能元件是同步器，从而识别对于从一个时钟环境传递到另一个时钟环境的信号是否存在同步问题。

公开(公告)号：US20050166106A1

公开(公告)日：2005-07-28

申请号：US11015749

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/28

CPC classification number: G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract translation: 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和要测试的电路之间的测试控制电路; 其中测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：US06903750B2

公开(公告)日：2005-06-07

申请号：US10117308

申请日：2002-04-05

Applicant: Nathan Mackenzie Sidwell

Inventor： Nathan Mackenzie Sidwell

IPC: G06T11/20 ,  G09G5/00

CPC classification number: G06T11/203

Abstract: A method for generating a series of digitized control values for an output device to represent a continuous series of source data, comprising the steps of: storing in a single register a first digitized control value and an indication of deviation between that value and the source data; and repeatedly adding an increment to the register to generate a further digitized control value and simultaneously update the indication of deviation.

Abstract translation: 一种用于为输出设备生成一系列数字化控制值以表示连续的源数据序列的方法，包括以下步骤：在单个寄存器中存储第一数字化控制值和该值与源数据之间的偏差指示 ; 并且向该寄存器反复增加一个增量以产生另一个数字化的控制值并且同时更新偏差的指示。

公开(公告)号：US06886156B2

公开(公告)日：2005-04-26

申请号：US09727327

申请日：2000-11-29

Applicant: Marian McCormack

Inventor： Marian McCormack

IPC: G06F9/44 ,  G06F9/445 ,  G06F9/45

CPC classification number: G06F8/54 ,  G06F8/53

Abstract: A method of disassembling object code to generate the original source code is discussed, together with a lister for performing the disassembly. The object code has relocation sections associated with some of the section data. For each location in the section data the lister determines if there is an associated relocation instruction and if there is, the lister derives certain additional information concerning the section data. The lister then generates the original source code, including the additional information.One example of the additional information is an arithmetic expression used to calculate a value in a relocation instruction. The set of relocations associated with the location of the instruction are read in turn by the lister and by using an expression calculator and an expression stack, the original arithmetic expression can be reconstructed.

Abstract translation: 与一个用于执行反汇编的列表一起讨论一种拆分目标代码以生成原始源代码的方法。 目标代码具有与部分数据相关联的重定位部分。 对于区段数据中的每个位置，列表器确定是否存在关联的重定位指令，并且如果存在，则列表将导出关于段数据的某些附加信息。 然后，列表生成原始源代码，包括附加信息。 附加信息的一个示例是用于计算重定位指令中的值的算术表达式。 与指令位置相关联的重定位集合由列表读取，并且通过使用表达式计算器和表达式堆栈，可以重构原始算术表达式。

公开(公告)号：US20050068091A1

公开(公告)日：2005-03-31

申请号：US10896371

申请日：2004-07-21

Applicant: Tahir Rashid

Inventor： Tahir Rashid

IPC: G05F3/20 ,  G05F3/26 ,  G05F3/02

CPC classification number: G05F3/265 ,  G05F3/205

Abstract: A biasing circuit comprising a first switching device having a control terminal, and first and second switching terminals. The first switching terminal being connected to a supply voltage, the second switching terminal being connected through a first resistive element to ground, and the control terminal being supplied by a reference voltage which is determined depending on the mode of operation of the circuit. The circuit further comprising a first branch connected between the control terminal and ground comprising a second resistive element in series with a second switching device. The second switching device forming part of a first current mirror having a second branch for effecting a generated bias value. During a normal mode of operation the reference voltage is dependant on the generated bias value, whereas during a standby mode of operation the reference voltage is connected to a low potential.

Abstract translation: 一种偏置电路，包括具有控制端子的第一开关器件，以及第一和第二开关端子。 第一开关端子连接到电源电压，第二开关端子通过第一电阻元件连接到地，并且控制端子由根据电路的操作模式确定的参考电压提供。 电路还包括连接在控制端和地之间的第一分支，包括与第二开关装置串联的第二电阻元件。 形成第一电流镜的一部分的第二开关器件具有用于产生所产生的偏置值的第二支路。 在正常工作模式下，参考电压取决于产生的偏置值，而在待机工作模式下，参考电压连接到低电位。

公开(公告)号：US06871266B2

公开(公告)日：2005-03-22

申请号：US10446280

申请日：2003-05-23

Applicant: Andrew Craig Sturges ,  David May

Inventor： Andrew Craig Sturges ,  David May

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC classification number: G06F12/0804 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1045

Abstract: A cache system is provided which includes a cache memory and a cache refill mechanism which allocates one or more of a set of cache partitions in the cache memory to an item in dependence on the address of the item in main memory. This is achieved in one of the described embodiments by including with the address of an item a set of partition selector bits which allow a partition mask to be generated to identify into which cache partition the item may be loaded.

公开(公告)号：US20050058185A1

公开(公告)日：2005-03-17

申请号：US10815167

申请日：2004-03-31

Applicant: Philip Mattos

Inventor： Philip Mattos

IPC: G01S1/00 ,  G01S19/21 ,  G01S19/30 ,  H04B1/707

CPC classification number: H04B1/707 ,  G01S19/21 ,  G01S19/30 ,  H04B2201/70715

Abstract: A method of acquiring a received broadcast signal that includes mixing the signal with a local frequency and digitizing the same to produce a received digitized signal, correlating the received digitized signal with a local version of a repeated code in the signal using a clock derived coherently from a master clock source and again for a second time period that is separated by a separation period for producing first and second results, and combining the first and second correlation results by comparing the location of correlation peaks to reject peaks not appearing at the same position in both the first and second correlation results.

Abstract translation: 一种获取接收到的广播信号的方法，包括将信号与本地频率进行混合并对其进行数字化以产生接收的数字化信号，将所接收的数字化信号与信号中的重复码的本地版本相关联， 主时钟源，并且再次为第二时间段分隔，用于产生第一和第二结果的分离周期;​​以及通过将相关峰的位置与不出现在相同位置处的峰值进行比较来组合第一和第二相关结果 第一和第二相关结果。

公开(公告)号：US06865623B2

公开(公告)日：2005-03-08

申请号：US10354908

申请日：2003-01-30

Applicant: Andrew Dellow

Inventor： Andrew Dellow

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A semiconductor integrated circuit for use in direct memory access (DMA) has two sources which communicate with a bus through a bus interface. A DMA access signal generator is coupled to the bus interface and asserts a DMA access output signal at a DMA access signal pin whenever either of the sources requires a DMA access. The need for separate DMA access signal pins for each of the two sources is thereby avoided. With targets on two separate integrated circuits, a single DMA access pin can be used for the two targets, while chip select signals at chip select pins on the source integrated circuit indicate which of the two targets is intended for the DMA access.

Abstract translation: 用于直接存储器访问（DMA）的半导体集成电路具有通过总线接口与总线通信的两个源。 DMA访问信号发生器耦合到总线接口，并且每当任何一个源需要DMA访问时，在DMA访问信号引脚处断言DMA访问输出信号。 因此避免了对于两个源中的每一个的单独的DMA访问信号引脚的需要。 通过两个独立的集成电路上的目标，两个目标可以使用单个DMA访问引脚，而源集成电路芯片选择引脚上的芯片选择信号指示两个目标中的哪一个用于DMA访问。

公开(公告)号：US06859932B1

公开(公告)日：2005-02-22

申请号：US09650033

申请日：2000-08-28

Applicant: Richard Shann

Inventor： Richard Shann

IPC: G06F9/445 ,  G06F9/00

CPC classification number: G06F8/54

Abstract: An executable program is prepared from a plurality of object code modules, each object code module including section data and associated relocations and at least one of the object code modules further including code sequences at least some of which are like to be repeatedly included in the executable program. Wherever a code sequence is to be inserted, a relocation instruction specifies the location of the code sequence and the code sequence is inserted into the section data at the appropriate point. A linker, a method for assembling, and a computer program product support these operations.

Abstract translation: 从多个目标代码模块准备可执行程序，每个对象代码模块包括段数据和关联的重定位，以及目标代码模块中的至少一个目标代码模块还包括代码序列，其中至少一些类似于要重复地包括在可执行程序中 程序。 无论何时插入代码序列，重定位指令指定代码序列的位置，代码序列在适当的位置插入到段数据中。 链接器，组装方法以及计算机程序产品支持这些操作。