公开(公告)号：US07536579B2

公开(公告)日：2009-05-19

申请号：US11462157

申请日：2006-08-03

Applicant: Wally Haas ,  Mutema John Pittman ,  Chuck Rumbolt

Inventor： Wally Haas ,  Mutema John Pittman ,  Chuck Rumbolt

IPC: G06F1/00 ,  H04L7/00 ,  G06F13/42 ,  G11B20/20 ,  H04B1/38

CPC classification number: H04L25/14 ,  H04L1/243

Abstract: An apparatus for determining the amount of skew to be injected for system skew compensation in a high-speed data communications system including a plurality of lanes with a data bus per lane. Such skew compensation is necessary due to inherent system skew. By iterating through the possible intervals within the maximum expected skew search space, the correct combination of search space intervals for all lanes can be determined to provide alignment and thus compliancy with relevant standards, such as the SFI-5 and SxI-5 standards, in terms of data skew specifications.

Abstract translation: 一种用于在包括具有每个通道的数据总线的多个通道的高速数据通信系统中确定要注入用于系统偏移补偿的偏斜量的装置。 由于固有的系统偏移，这种偏斜补偿是必要的。 通过迭代最大预期偏斜搜索空间内的可能间隔，可以确定所有通道的搜索空间间隔的正确组合，以提供一致性，从而符合相关标准，如SFI-5和SxI-5标准 数据偏移规范。

公开(公告)号：US20090031065A1

公开(公告)日：2009-01-29

申请号：US12219565

申请日：2008-07-24

Applicant: James Denis Travers ,  Padraig Ryan

Inventor： James Denis Travers ,  Padraig Ryan

IPC: G06F13/14

CPC classification number: H04L1/243 ,  H04L1/205

Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract translation: 描述用于连接诸如I2C总线的两个有线和总线的数字位级中继器。 协议检测器用于跟踪时钟和数据信号以确定传输的方向。 状态机读取并重新生成两条总线的时钟线，并在两条总线上提供时钟延伸协议功能。 中继器被设计为在可能时将数据位从一个总线传输到另一个总线，并且锁存和保持每个数据位，直到当时钟延长发生时或当总线转向时才能对接收总线进行时钟控制。

公开(公告)号：US20080205286A1

公开(公告)日：2008-08-28

申请号：US11710495

申请日：2007-02-26

Applicant: Gui-He Li ,  Tom Chen ,  Win-Harn Liu

Inventor： Gui-He Li ,  Tom Chen ,  Win-Harn Liu

IPC: H04L1/14

CPC classification number: H04L1/243

Abstract: A test system using a local loop to establish connection to baseboard management control is provided. The test system includes more than one host terminals having at least one network interface card (NIC) and at least one baseboard management controller (BMC) having one NIC. After establishing a connection for test between the host terminals and a remote subscriber, a connection for loop test is established with the BMC through a virtual address, so as to deliver a test instruction to the BMC for testing and to loop back a test result. The test system establishes the connection for loop test through the virtual address so as to perform a remote platform test similar to an inner loop test. Therefore, the test result will not be influenced by a network environment setting, and thus a batch test can be adopted to save the test time.

Abstract translation: 提供了使用本地环路建立与基板管理控制连接的测试系统。 测试系统包括具有至少一个网络接口卡（NIC）的多个主机终端和具有一个NIC的至少一个基板管理控制器（BMC）。 在主机终端和远程用户建立测试连接后，通过虚拟地址与BMC建立环路测试连接，以便向BMC发送测试指令以进行测试并循环测试结果。 测试系统通过虚拟地址建立循环测试的连接，以便执行类似于内环测试的远程平台测试。 因此，测试结果不会受到网络环境设置的影响，因此可以采用批量测试来节省测试时间。

公开(公告)号：US07408883B2

公开(公告)日：2008-08-05

申请号：US10931483

申请日：2004-09-01

Applicant: Aaron Thomas Deragon ,  Gregory John Soule

Inventor： Aaron Thomas Deragon ,  Gregory John Soule

IPC: H04L1/24

CPC classification number: H04L12/4645 ,  H04L1/243 ,  H04L43/50

Abstract: The invention is test apparatus and methods for performing loopback tests. The tests involve generating a packet-based test message having a source address and a destination address. When the test message arrives at the destination, the addresses are exchanged and the message is returned to the source. The addresses can be level 2 addresses, such as MAC addresses, and/or level 3 addresses, such as IP addresses. The returned message and the propagation properties observed for the test message can be used to determine information about the network being tested.

Abstract translation: 本发明是用于进行环回测试的测试装置和方法。 测试涉及产生具有源地址和目的地地址的基于分组的测试消息。 当测试消息到达目的地时，交换地址并将消息返回给源。 地址可以是2级地址，如MAC地址和/或3级地址，如IP地址。 可以使用返回的消息和测试消息观察到的传播属性来确定有关正在测试的网络的信息。

公开(公告)号：US20080141074A1

公开(公告)日：2008-06-12

申请号：US11976544

申请日：2007-10-25

Applicant: Kaoru Noumi ,  Susumu Nishihashi ,  Tomoyuki Katou ,  Yukio Ishikawa ,  Yasuyuki Umezaki ,  Hidetaka Ebeshu ,  Shigeo Koide ,  Yukio Fujisawa ,  Hiroaki Shimauchi

Inventor： Kaoru Noumi ,  Susumu Nishihashi ,  Tomoyuki Katou ,  Yukio Ishikawa ,  Yasuyuki Umezaki ,  Hidetaka Ebeshu ,  Shigeo Koide ,  Yukio Fujisawa ,  Hiroaki Shimauchi

IPC: G06F11/00

CPC classification number: H04L1/0045 ,  G06F11/10 ,  H04L1/0063 ,  H04L1/243 ,  H04L1/244

Abstract: An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.

Abstract translation: 错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及 选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。 当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断 。

公开(公告)号：US07385991B2

公开(公告)日：2008-06-10

申请号：US10154586

申请日：2002-05-24

Applicant: Carlos G. Carvajal ,  L. Grant Giddens ,  Dieter H. Nattkemper ,  Robert S. Kroninger

Inventor： Carlos G. Carvajal ,  L. Grant Giddens ,  Dieter H. Nattkemper ,  Robert S. Kroninger

IPC: H04L12/28

CPC classification number: H04L1/243

Abstract: A method for processing cells at a user-network interface with automatic identification of virtual circuit identifiers and a testing function is provided. The method includes distinguishing the source of the cell. When the cell is from a first source, the method tests the cell against at least one selected criteria. When at least one test determines the cell is invalid, the cell is marked. When the tests determine that the cell is valid, the method translates a virtual circuit identifier to a default setting and forwards the cell to a queue for further processing.

Abstract translation: 提供了一种在用户网络接口处处理单元的方法，其中虚拟电路标识符的自动识别和测试功能。 该方法包括区分细胞的来源。 当单元格来自第一个源时，该方法将根据至少一个选定的标准来测试单元格。 当至少一个测试确定单元格无效时，单元格被标记。 当测试确定单元格有效时，该方法将虚拟电路标识符转换为默认设置，并将该单元转发到队列以进行进一步处理。

公开(公告)号：US07346004B2

公开(公告)日：2008-03-18

申请号：US10358340

申请日：2003-02-05

Applicant: Yoon-Jin Ku ,  Young-Seok Kim

Inventor： Yoon-Jin Ku ,  Young-Seok Kim

IPC: H04L1/00

CPC classification number: H04L1/243

Abstract: Disclosed is a method for setting a transfer mode in a line interface device for supporting at least two modes. The method for automatically setting a data transfer mode of a line interface device includes the steps of: a) reading all modes supportable in a line interface mode, generating a test message for requesting a loopback operation according to the order of the read modes, and transmitting the test message via a transmission line; b) upon receiving the test message within a predetermined period of time, setting a transfer mode used for transferring the test message to a data conversion mode of the line interface device, and informing a main controller of the system of the data conversion mode setup; c) repeatedly performing the steps (a) and (b) to set the next mode according to the order of the modes, if the test message for requesting the loopback operation message is not received within the predetermined period of time; and d) transmitting a mode setup denial message to the main controller of the system, if it is impossible to set a mode after a mode setup trial has been applied to all the read modes.

Abstract translation: 公开了一种用于设置用于支持至少两种模式的线路接口装置中的传送模式的方法。 用于自动设置线路接口设备的数据传输模式的方法包括以下步骤：a）读取在线路接口模式下可支持的所有模式，根据读取模式的顺序产生用于请求环回操作的测试消息;以及 通过传输线发送测试消息; b）在预定时段内收到测试消息后，将用于传送测试消息的传送模式设置为线路接口设备的数据转换模式，并向系统的主控制器通知数据转换模式设置; c）如果在预定时间段内没有接收到用于请求回送操作消息的测试消息，则重复执行步骤（a）和（b）以根据模式的顺序设置下一个模式; 以及d）如果在模式设置试用已应用于所有读取模式之后不可能设置模式，则将模式设置拒绝消息发送到系统的主控制器。

公开(公告)号：US07337377B2

公开(公告)日：2008-02-26

申请号：US11315974

申请日：2005-12-22

Applicant: Michael C. Panis ,  Bradford B. Robbins

Inventor： Michael C. Panis ,  Bradford B. Robbins

IPC: G01R31/28

CPC classification number: G01R31/31716 ,  G01R31/3004 ,  G01R31/3016 ,  H04L1/243

Abstract: A system and method for economically yet thoroughly testing serial ports of electronic devices includes a receiver and a transmitter. The receiver is coupled to a TX line of a device under test for receiving an input serial bit stream from the device under test. The transmitter is coupled to a RX line of the device under test for providing an output serial bit stream to the device under test. The receiver is coupled to the transmitter for establishing a loopback connection. A time distortion circuit is interposed between the receiver and the transmitter, for adding predetermined amounts of timing distortion to the output serial bit stream. In addition, a selector is interposed between the receiver and the transmitter, for selecting between the receiver and a direct input. The direct input provides an algorithmic test signal that differs from the input serial bit stream received by the receiver. The direct input thus allows a tester to exercise the device under test with a test signal that differs from the signal that the device under test generates. A time measurement circuit measures timing characteristics of the device under test, and a parametric measurement circuit measures steady-state characteristics of the device under test.

Abstract translation: 用于经济地彻底测试电子设备的串行端口的系统和方法包括接收机和发射机。 接收器耦合到被测设备的TX线路，用于接收来自被测器件的输入串行比特流。 发射机耦合到被测设备的RX线路，以向被测设备提供输出串行比特流。 接收机耦合到发射机，用于建立环回连接。 时间失真电路插在接收机和发射机之间，用于将预定量的定时失真加到输出串行比特流。 此外，选择器插在接收器和发射器之间，用于在接收器和直接输入之间进行选择。 直接输入提供与接收机接收的输入串行比特流不同的算法测试信号。 因此，直接输入允许测试者使用与被测器件产生的信号不同的测试信号来锻炼被测器件。 时间测量电路测量被测器件的定时特性，参数测量电路测量被测器件的稳态特性。

公开(公告)号：US20080031312A1

公开(公告)日：2008-02-07

申请号：US11462157

申请日：2006-08-03

Applicant: Wally Haas ,  Mutema Pittman ,  Chuck Rumbolt

Inventor： Wally Haas ,  Mutema Pittman ,  Chuck Rumbolt

IPC: H04L5/16

CPC classification number: H04L25/14 ,  H04L1/243

Abstract: This algorithm and apparatus provides the ability to deskew a plurality of lanes comprising a data bus in a high-speed data communications system. This deskewing is necessary due to inherent system skew. By iterating through the possible intervals within the maximum expected skew search space, the correct combination of search space intervals for all lanes can be determined to provide alignment and thus compliancy with relevant standards, such as the SxI-5 standard, in terms of data skew specifications.

Abstract translation: 该算法和装置提供了在高速数据通信系统中对包括数据总线的多条通道进行偏斜校正的能力。 由于固有的系统偏差，这种去歪斜是必要的。 通过迭代最大预期偏斜搜索空间内的可能间隔，可以确定所有通道的搜索空间间隔的正确组合，以提供对齐方式，从而在数据偏移方面提供相关标准，如SxI-5标准 规格。

公开(公告)号：US20080024170A1

公开(公告)日：2008-01-31

申请号：US11869115

申请日：2007-10-09

Applicant: Michael Kerr ,  William Lawson

Inventor： Michael Kerr ,  William Lawson

IPC: H03K19/094

CPC classification number: H04L25/0292 ,  H04L1/243 ,  H04L25/0272

Abstract: A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

Abstract translation: 体现在设计过程中使用的机器可读介质中的设计结构包括第一网络组件和第二网络组件之间的高速接口，该接口包括用于接收的正电压输入（VINP）和负电压输入（VINN） 来自第一网络组件的输入数据信号; 通过正输入总线和负输入总线耦合到负输出电路（OUTN）和负电压输入（VINN）的正电压输入（VINP），负电压输入（VINN）也耦合到正输出电路 OUTP）。 实施高速接口要求对正输入总线和负输入总线施加偏置，以周期性地复用数据信号，从而提供用于功能数据的公共接收路径并包裹数据信号的数据。