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公开(公告)号:US11409665B1
公开(公告)日:2022-08-09
申请号:US17315575
申请日:2021-05-10
发明人: Bo Fu , Lin Chen , Jie Chen , Cheng-Yun Hsu
IPC分类号: G06F12/109 , G06F12/1009
摘要: Systems, apparatus and methods are provided for using a partial logical-to-physical (L2P) address translation table for multiple namespaces to perform address translation. An exemplary embodiment may provide a method comprising: receiving a request for a first logical data address (LDA) that belongs to a first namespace (NS); searching the first NS in an entry location table (ELT) for all namespaces whose L2P entries always reside in memory; determining that the first NS is not in the ELT; searching a cache of lookup directory entries of recently accessed translation data units (TDUs) for a first TDU containing a L2P entry for the first LDA; determining that there is a cache miss; retrieving the lookup directory entry for the first TDU from an in-memory lookup directory and determining that it is not valid; reserving a TDU space for the first TDU; and generating a load request for the first TDU.
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公开(公告)号:US20220179863A1
公开(公告)日:2022-06-09
申请号:US17679835
申请日:2022-02-24
申请人: Ocient Inc.
发明人: George Kondiles , Jason Arnold
IPC分类号: G06F16/2453 , G06F16/22 , G06F16/2455 , G06F16/901 , G06F9/4401 , G06F9/50 , H04L67/10 , G06F3/06 , G06F12/0893 , G06F16/17 , G06F11/10 , G06F12/109 , G06F16/23 , G06F16/242 , H03M7/30 , G06F16/2457 , G06F16/2458 , G06F16/27 , G06F7/24
摘要: A method includes generating a plurality of parity blocks from a plurality of lines of data blocks. The plurality of lines of data blocks are stored in data sections of memory of a cluster of computing devices of the computing system by distributing storage of individual data blocks of the plurality of lines of data blocks among unique data sections of the cluster of computing devices. The plurality of parity blocks are stored in parity sections of memory of the cluster of computing devices by distributing storage of parity blocks of the plurality of parity blocks among unique parity sections of the cluster of computing devices.
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公开(公告)号:US11347658B1
公开(公告)日:2022-05-31
申请号:US17513776
申请日:2021-10-28
发明人: Robert Lercari , Alan Chen , Mike Jadon , Craig Robertson , Andrey V. Kuzmin
IPC分类号: G06F12/1009 , G06F3/06 , G06F12/109 , G06F12/02
摘要: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
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34.
公开(公告)号:US11347656B1
公开(公告)日:2022-05-31
申请号:US17479444
申请日:2021-09-20
发明人: Robert Lercari , Alan Chen , Mike Jadon , Craig Robertson , Andrey V. Kuzmin
IPC分类号: G06F12/1009 , G06F3/06 , G06F12/109 , G06F12/02
摘要: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
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公开(公告)号:US20220138027A1
公开(公告)日:2022-05-05
申请号:US17429889
申请日:2020-02-05
发明人: Rene Graf
IPC分类号: G06F9/54 , G06F12/0802 , G06F12/109
摘要: In a method for transmitting a message in a computing system, the message is transmitted by a transmitter and received by a receiver. The transmitter is granted access to a memory area for the purpose of transmitting using a first virtual address allocated to the transmitter by a memory management unit, whereas the access to the memory area by the transmitter is revoked after transmitting. Subsequently, the receiver is granted access to the memory area for the purpose of receiving using a second virtual address allocated to the receiver by a memory management unit. The first virtual address may be different from the second virtual address.
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公开(公告)号:US11307992B2
公开(公告)日:2022-04-19
申请号:US16164252
申请日:2018-10-18
申请人: Silicon Motion, Inc.
发明人: Sheng-Liu Lin
IPC分类号: G06F12/1009 , G06F12/109
摘要: The invention introduces a method for performing operations to namespaces of a flash memory device, at least including the steps: receiving a namespace setting-update command from a host, requesting to update a namespace size of a namespace; determining whether the updated namespace size of the namespace can be supported; and when the updated namespace size of the namespace can be supported, updating a logical-physical mapping table of the namespace to enable the namespace to store user data of the updated namespace size.
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公开(公告)号:US11301392B2
公开(公告)日:2022-04-12
申请号:US17063888
申请日:2020-10-06
IPC分类号: G06F12/10 , G06F12/02 , G06F12/109 , G06F12/1036
摘要: A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.
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公开(公告)号:US11294902B2
公开(公告)日:2022-04-05
申请号:US17091195
申请日:2020-11-06
申请人: Ocient Inc.
发明人: George Kondiles , Jason Arnold
IPC分类号: G06F16/2453 , G06F16/22 , G06F16/2455 , G06F16/901 , G06F9/4401 , G06F9/50 , H04L67/10 , G06F3/06 , G06F12/0893 , G06F16/17 , G06F11/10 , G06F12/109 , G06F16/23 , G06F16/242 , H03M7/30 , G06F16/2457 , G06F16/2458 , G06F16/27 , G06F7/24
摘要: A method includes generating, by a processing entity of a computing system, a plurality of parity blocks from a plurality of lines of data blocks. A first number of parity blocks of the plurality of parity blocks is generated from a first line of data blocks of the plurality of lines of data blocks. The method further includes storing, by the processing entity, the plurality of lines of data blocks in data sections of memory of a cluster of computing devices of the computing system in accordance with a read/write balancing pattern and a restricted file system. The method further includes storing, by the processing entity, the plurality of parity blocks in parity sections of memory of the cluster of computing devices in accordance with the read/write balancing pattern and the restricted file system.
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公开(公告)号:US20220091996A1
公开(公告)日:2022-03-24
申请号:US17539896
申请日:2021-12-01
申请人: Nutanix, Inc.
发明人: Karan Gupta , Gowtham Alluri , Dheer Moghe , Anshul Purohit , Arth Patel , Ajay Raghavan , Roger Liao
IPC分类号: G06F12/109 , G06F3/06
摘要: An illustrative embodiment disclosed herein is an apparatus including a processor and a memory. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to store a first object and a second object in a first region based on the first object and the second object having a first policy. In some embodiments, the memory includes programmed instructions that, when executed by the processor, cause the apparatus to store a third object in a second region based on the third object having a second policy. In some embodiments, a virtual disk includes the first region and the second region.
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公开(公告)号:US11221944B1
公开(公告)日:2022-01-11
申请号:US17002667
申请日:2020-08-25
申请人: VMware, Inc.
发明人: Wenguang Wang , Vamsi Gunturu , Junlong Gao , Ilya Languev , Petr Vandrovec , Maxime Austruy , Ilia Sokolinski , Satish Pudi
IPC分类号: G06F12/12 , G06F12/02 , G06F12/109
摘要: A method for managing metadata for data stored in a cloud storage is provided. The method receives, at a first of a plurality of metadata servers, information associated with an object stored in the cloud storage, the information comprising a plurality of LBAs for where the object is stored. Each metadata server allocates contiguous chunk IDs for a group of objects. The method generates a new chunk ID for the object, which is a combination of a unique fixed value and a monotonically incrementing local value associated with each LBA, such that a first LBA is mapped to a first chunk ID having a first local value and a next LBA is mapped to a second chunk ID having the first local value incremented as a second local value. The method stores the new chunk ID and other metadata in one or more tables stored in a metadata storage.
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