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246 条记录 (耗时 0.013 秒)

    Circuit arrangement for generating a sampling pulse raster adapted to the variable period of quasiperiodic events
    31.
    发明授权
    Circuit arrangement for generating a sampling pulse raster adapted to the variable period of quasiperiodic events 失效
    用于产生适应于准周期事件的可变周期的采样脉冲光栅的电路装置

    公开(公告)号：US3982193A

    公开(公告)日：1976-09-21

    申请号：US534832

    申请日：1974-12-20

    申请人： Albert Maringer

    发明人： Albert Maringer

    IPC分类号： F02P17/02 ,  G01R13/34 ,  H03K3/64 ,  H03K3/84 ,  H03K3/72 ,  H03K21/30

    CPC分类号： G01R13/34 ,  F02P17/02 ,  H03K3/64

    摘要： The invention is a circuit for generating a sampling pulse raster which has a pulse repetition frequency proportional to periodic events with variable period, which are to be sampled. The sampling pulses can be taken off at the counting stages of a pulse counter the counting input of which is connected to the output of a voltage-frequency converter. The voltage-frequency converter has two inputs: one for a voltage proportional to the period of the periodic events; another for a voltage proportional to the selected number of sampling pulses per period. The first voltage controls the frequency of the output pulses of the voltage-frequency converter in an inversely proportional sense.

    摘要翻译： 本发明是用于产生采样脉冲光栅的电路，其具有与可变周期的周期性事件成比例的脉冲重复频率，其将被采样。 采样脉冲可以在其计数输入连接到电压 - 频率转换器的输出的脉冲计数器的计数阶段被取消。 电压 - 频率转换器有两个输入：一个用于与周期性事件周期成比例的电压; 另一个与每个周期选择的采样脉冲数成比例的电压。 第一电压以反比例的方式控制电压 - 频率转换器的输出脉冲的频率。

    Phase shifting circuit
    32.
    发明授权
    Phase shifting circuit 失效
    移相电路

    公开(公告)号：US3935483A

    公开(公告)日：1976-01-27

    申请号：US445159

    申请日：1974-02-25

    申请人： Kazuyuki Arimoto ,  Toshinobu Maeda ,  Fuzio Hori ,  Akihiko Takata

    发明人： Kazuyuki Arimoto ,  Toshinobu Maeda ,  Fuzio Hori ,  Akihiko Takata

    IPC分类号： H03K5/04 ,  G05F1/10 ,  H03K3/64 ,  H03K3/72 ,  H03K5/00 ,  H03K5/13 ,  H03K1/16

    CPC分类号： H03K5/13 ,  H03K2005/00286

    摘要： A phase shifting circuit having a first delay element with a time constant .tau..sub.1, a second delay element with a time constant .tau..sub.2 smaller than .tau..sub.1 and a pulse generating element such as p-n-p-n transistor produces phase shifting pulses with respect to a reference phase upon application of a step-up voltage to the first delay element and periodic pulses to the second delay element. The two signals rise at different rate following respective curves and the two curves intersect at various points. The pulses generating element compares the two signals and produces a pulse at the instant the two signals coincides at the intersecting points. The phase shifting pulses have a linear phase relation with respect to the reference phase which is equal to the phase of the periodic pulses applied to the second delay element.

    摘要翻译： 一种具有时间常数τ1的第一延迟元件，具有小于τ1的时间常数τ2的第二延迟元件和诸如pnpn晶体管的脉冲产生元件的相移电路产生相对于基准相位的相移脉冲 对第一延迟元件施加升压电压并向第二延迟元件施加周期性脉冲。 两个信号在各曲线之后以不同的速率上升，两条曲线在各个点处相交。 脉冲发生元件比较两个信号，并且在两个信号在相交点处重合的瞬间产生脉冲。 相移脉冲相对于等于施加到第二延迟元件的周期性脉冲的相位的参考相位具有线性相位关系。

    Generator for short-duration high-frequency pulse signals
    33.
    发明授权
    Generator for short-duration high-frequency pulse signals 失效
    短时脉冲高频脉冲信号发生器

    公开(公告)号：US3612899A

    公开(公告)日：1971-10-12

    申请号：US3612899D

    申请日：1970-08-20

    申请人： SPERRY RAND CORP

    发明人： ROSS GERALD F ,  LORENZO JOSEPH D DE

    IPC分类号： H03K3/80 ,  H03K3/64

    CPC分类号： H03K3/80

    摘要： Very narrow pulses of high-frequency sine wave electromagnetic energy are formed by use of a gated or pulse modulated continuous-wave source feeding a transmission line network having a time-limited impulse response and adjusted to provide a series resonance with the leakage capacity of the source gating or modulating switch for the purpose of assuring that a maximum of the available energy is employed to form the output and that the output level is nulled before and after the generation of the high-frequency pulse.

    Word pulse generating devices using successive delay for pulse formation
    34.
    发明授权
    Word pulse generating devices using successive delay for pulse formation 失效
    使用连续延迟脉冲形成的WORD脉冲发生器件

    公开(公告)号：US3609404A

    公开(公告)日：1971-09-28

    申请号：US3609404D

    申请日：1969-09-15

    申请人： IWATSU ELECTRIC CO LTD

    发明人： UCHIDA KOZO

    IPC分类号： G11C17/08 ,  H03K3/64 ,  H03K5/00

    CPC分类号： H03K3/64 ,  G11C17/08

    摘要： A clock pulse generator for word pulses is comprised of a signal generator, a distributor to divide the signal generated by the signal generator into a plurality of outputs, a plurality of parallel circuits connected to receive the divided signals, each circuit including a serially connected delay circuit and a pulser, and a mixer to combine outputs from the parallel circuits characterized in that the respective parallel circuits have equal delay time difference.

    Trigger pulse circuits
    35.
    发明授权
    Trigger pulse circuits 失效
    触发脉冲电路

    公开(公告)号：US3584240A

    公开(公告)日：1971-06-08

    申请号：US3584240D

    申请日：1969-04-02

    申请人： RCA CORP

    发明人： HOFFMAN KARL H

    IPC分类号： H03K3/351 ,  H03K3/64

    CPC分类号： H03K3/351

    摘要： A charge storage means, such as a capacitor, and a switch, such as the emitter-to-base diode of a unijunction transistor connected across the capacitor. To prevent the capacitor from discharging prematurely, a valve, such as a second capacitor, is placed in series therewith in the charging circuit thereof. The values of the capacitors can be so chosen that once the first one discharges into the emitter-to-base diode circuit, it cannot again charge to the firing potential of this unijunction transistor until the second capacitor independently is discharged.

    Synchronizing clock system
    36.
    发明授权
    Synchronizing clock system 失效
    同步时钟系统

    公开(公告)号：US3577128A

    公开(公告)日：1971-05-04

    申请号：US3577128D

    申请日：1969-01-14

    申请人： IBM

    发明人： CRISCIMAGNA TONY N ,  FOURNIER ROBERT J

    IPC分类号： G06F13/10 ,  G04G7/00 ,  G06F1/10 ,  G06F1/12 ,  G06F3/06 ,  H04L7/033 ,  H04L7/04 ,  H03K3/64

    CPC分类号： G06F1/10 ,  G04G7/00

    摘要： In a data processing system, apparatus for synchronizing a slave clock in an input/output device with a master clock in a central processing unit. A set of clock signals from a CPU are received in parallel, converted to serial and pulses are generated in response to the leading and trailing edge of each of the series of signals. The series of pulses is then delayed and shaped to drive a slaved I/O clock. A delay line is adjusted so that the total equivalent system delay is equal to an integral number of CPU pulse durations.

    Delay line control gated micrologic clock generator
    37.
    发明授权
    Delay line control gated micrologic clock generator 失效
    延迟线控制门控时钟发生器

    公开(公告)号：US3562558A

    公开(公告)日：1971-02-09

    申请号：US3562558D

    申请日：1968-10-21

    申请人： COLLINS RADIO CO

    发明人： TOTTEN FLOYD M

    IPC分类号： H03K3/03 ,  H03K3/64 ,  H03K5/00

    CPC分类号： H03K3/64 ,  H03K3/03 ,  Y10S331/03

    摘要： A delay line and logic control gated micrologic circuit clock signal pulse train generator with each pulse waveform clock signal in synchronism with its initiating gate trigger signal. A NAND gate receives an activating gate trigger signal and immediately a voltage shift in NAND gate output with this is then passed through a delay line coil both to output path means and also back as an additional input inhibit for the NAND gate at a predetermined delay determined by the delay line. The immediately resulting voltage shift at the NAND gate output is again passed through the delay line coil with the same delay to then remove the inhibit signal from the NAND gate with again an immediate shift in the NAND gate output voltage, and with the pulse generating cycle continually repeating itself with precise pulse width and spacing between pulses in a pulse train in synchronism although delayed from the start of the activating gate trigger signal with the pulse train cycle generating action continued just so long as the activating gate trigger signal is applied.