公开(公告)号：US11038032B2

公开(公告)日：2021-06-15

申请号：US16990606

申请日：2020-08-11

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Vincenzo Enea

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/40 ,  H01L21/266 ,  H01L21/265

Abstract: A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

公开(公告)号：US20210175753A1

公开(公告)日：2021-06-10

申请号：US17109345

申请日：2020-12-02

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto LA ROSA ,  Alessandro FINOCCHIARO

IPC: H02J50/27 ,  H02J50/00 ,  H04B5/00

Abstract: A first RF-to-DC circuit receives a radiofrequency signal and produces a first converted signal delivered to an energy storage circuit. A second RF-to-DC circuit, which is a down-scaled replica of the first RF-to-DC circuit, produces a second converted signal from the radiofrequency signal that is indicative of an open-circuit voltage of the first RF-to-DC circuit. The first RF-to-DC section includes N sub-stages, with a sub-set of sub-stages being selectively activatable. A window comparison of the second converted signal generates a first signal and a second signal indicative of whether the second converted signal is within a range of values proportional to a voltage reference signal. The sub-set of sub-stages is selectively deactivated, respectively activated, when the performed window comparison has a first result, respectively, a second result.

公开(公告)号：US20210175350A1

公开(公告)日：2021-06-10

申请号：US17116465

申请日：2020-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando IUCOLANO ,  Alessandro Chini

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

公开(公告)号：US11032067B2

公开(公告)日：2021-06-08

申请号：US16022110

申请日：2018-06-28

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics S.r.l.

Inventor： Roberto Colombo ,  Guido Marco Bertoni ,  William Orlando ,  Roberta Vittimani

IPC: H04L9/08 ,  G06F13/36 ,  H04L9/14 ,  H04L9/32

Abstract: A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.

公开(公告)号：US20210167022A1

公开(公告)日：2021-06-03

申请号：US17108187

申请日：2020-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： Paolo CREMA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A leadframe has a die pad area and an outer layer of a first metal having a first oxidation potential. The leadframe is placed in contact with a solution containing a second metal having a second oxidation potential, the second oxidation potential being more negative than the first oxidation potential. Radiation energy is then applied to the die pad area of the leadframe contacted with the solution to cause a local increase in temperature of the leadframe. As a result of the temperature increase, a layer of said second metal is selectively provided at the die pad area of the leadframe by a galvanic displacement reaction. An oxidation of the outer layer of the leadframe is then performed to provide an enhancing layer which counters device package delamination.

公开(公告)号：US20210167000A1

公开(公告)日：2021-06-03

申请号：US17108270

申请日：2020-12-01

Applicant: STMicroelectronics S.r.l.

Inventor： Federico Giovanni ZIGLIOLI ,  Alberto PINTUS ,  Pierangelo MAGNI

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

公开(公告)号：US20210158190A1

公开(公告)日：2021-05-27

申请号：US17099582

申请日：2020-11-16

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Stefano Paolo RIVOLTA ,  Lorenzo BRACCO ,  Roberto MURA ,  Federico RIZZARDINI

IPC: G06N5/04 ,  G06K9/62 ,  G06N20/00

Abstract: A microelectromechanical weather pattern recognition system includes: at least one movement sensor, of a MEMS type, which generates a movement signal, in the presence and as a function of at least one weather pattern to be recognized; and a recognition circuitry, which is coupled to the movement sensor and which receives the movement signal; extracts given features of the movement signal; and perform processing operations, based on the given features of the movement signal, in order to recognize the weather pattern by executing at least one, appropriately trained, machine-learning algorithm.

公开(公告)号：US20210154820A1

公开(公告)日：2021-05-27

申请号：US16696772

申请日：2019-11-26

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC.

Inventor： Marco BIANCO ,  Lorenzo BRACCO ,  Mahesh CHOWDHARY ,  Roberto MURA ,  Stefano Paolo RIVOLTA ,  Federico RIZZARDINI

IPC: B25F5/00 ,  G01C19/00 ,  B23B45/00

Abstract: A device for generating a control signal based on the linear movement of a linear member is provided. The device includes a linear member, a rotatable member, a first inertial measurement unit (IMU) coupled to the rotatable member and a second IMU having a fixed position. The device also includes a processing circuit which uses sensing signals from the IMUS to determine an attitude of the first IMU referenced to the second IMU and generate a control signal based on the attitude.

公开(公告)号：US11018578B1

公开(公告)日：2021-05-25

申请号：US16671002

申请日：2019-10-31

Applicant: STMicroelectronics S.R.L.

Inventor： Alberto Bianco ,  Giuseppe Scappatura ,  Francesco Ciappa

IPC: H02M3/156 ,  H02M3/07

Abstract: An electronic device includes a circuit board that manages supply of electricity to the electronic device. The circuit board includes an integrated circuit and an external capacitor coupled to a supply terminal of the circuit board. During a startup operation of the integrated circuit, the integrated circuit supplies a first charging current to charge the capacitor to a supply voltage value. The circuit board includes a boost circuit that receives a portion of the first charging current and outputs a second charging current that augments charging of the capacitor. The second charging current is an amplification of the first charging current. The integrated circuit enables operation of the electronic device after the capacitor is charged to the supply voltage value.

公开(公告)号：US11018008B2

公开(公告)日：2021-05-25

申请号：US16209680

申请日：2018-12-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Edoardo Zanetti ,  Simone Rascuná ,  Mario Giuseppe Saggio ,  Alfio Guarnera ,  Leonardo Fragapane ,  Cristina Tringali

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/872 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.