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公开(公告)号：US20250081853A1
公开(公告)日：2025-03-06
申请号：US18819799
申请日：2024-08-29
Applicant: STMicroelectronics International N.V.
Inventor： Christian VERRENGIA CAPOROSSI , Annachiara ESPOSITO , Paola Sabrina BARBATO , Valeria CASUSCELLI , Rossana SCALDAFERRI
IPC: H10N30/85 , C08K3/22 , C09D5/24 , C09D7/40 , C09D7/61 , C09D127/16 , H04R17/02 , H10N30/092
Abstract: Composite material comprising a fluoropolymer matrix and a filler formed of nanoparticles of a ceramic of the BZT-αBXT type wherein X is selected from Ca, Sn, and Mn and a is a molar fraction selected in the range between 0.10-0.90 doped with at least one doping element selected from the group consisting of Nb, La, Mn, Nd and W, wherein when X is Mn, the doping element is not Mn, wherein said nanoparticles have an average diameter comprised between 10 and 25% by weight on the total weight of the composite. The composite material is used to form a thin film usable as a piezoelectric material with inductive properties in electronic components, for example acoustic sensors such as microphones, and energy harvesting transducers.
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公开(公告)号：US20250081627A1
公开(公告)日：2025-03-06
申请号：US18820139
申请日：2024-08-29
Applicant: STMicroelectronics International N.V.
Inventor： Chloe TROUSSIER , Johan BOURGEAT
IPC: H01L27/02
Abstract: An ESD protection device includes at least one semiconductor electronic switch electrically coupled in parallel with a diode. The semiconductor electronic switch and the diode each include at least one finger extending substantially parallel to a first direction. The fingers of the semiconductor electronic switch and of the diode are aligned with each other along this first direction.
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公开(公告)号：US20250080118A1
公开(公告)日：2025-03-06
申请号：US18241813
申请日：2023-09-01
Applicant: STMicroelectronics International N.V.
Inventor： Marco PASOTTI , Riccardo ZURLA , Marcella CARISSIMI , Riccardo VIGNALI , Alessandro CABRINI
IPC: H03K21/02
Abstract: An in-memory computation circuit includes a memory array with memory cells arranged in a matrix in rows and columns. Groups of memory cells store computational weights for an in-memory compute (IMC) operation that is performed with a first multiply and accumulate (MAC) elaboration to produce a first analog signal and a second MAC elaboration to produce a second analog signal. An analog-to-digital converter circuit operates to: increment a count value in a counter circuit in response to the first analog signal; convert the count value in the counter circuit to a negated count value; and increment the count value in the counter circuit starting from the negated count value in response to the second analog signal.
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公开(公告)号：US20250080072A1
公开(公告)日：2025-03-06
申请号：US18812704
申请日：2024-08-22
Applicant: STMicroelectronics International N.V.
Inventor： Franck MONTAUDON , Mounir BOULEMNAKHER , Julien GOULIER
IPC: H03F3/45
Abstract: An amplification circuit includes an amplifier circuit (provided by an operational amplifier) that amplifies a signal to be demodulated. A feedback loop of the amplification circuit has a resistance value that is controlled to discretely vary according to a level of an output node of the amplifier circuit. A comparison of the output level with respect to one or a plurality of thresholds, which define out-of-saturation operating ranges of the amplifier circuit, drives selection of the resistance value.
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公开(公告)号：US20250079992A1
公开(公告)日：2025-03-06
申请号：US18769734
申请日：2024-07-11
Applicant: STMicroelectronics International N.V.
Inventor： Ivan Floriani
Abstract: Control device for a switching voltage regulator. A control loop circuit generates a control signal indicative of the difference between the output voltage of a switching circuit and a nominal voltage. A drive signal generator is coupled to the control loop circuit and receives a measurement signal indicative of the current flowing in the switching circuit. The drive signal generator also receives a reference signal correlated to the control signal and generates pulse-width modulated switching signals for the switching circuit to maintain the output voltage at a regulated value. The drive signal generator compares the measurement signal with the reference signal at the peaks of the measurement signal in the first measurement mode and at the valleys of the measurement signal in the second. An offset generator generates an offset signal which is added to the control signal at a transition between the first and the second measurement modes.
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Patent Agency Ranking
公开(公告)号：US20250079991A1
公开(公告)日：2025-03-06
申请号：US18240459
申请日：2023-08-31
Applicant: STMicroelectronics International N.V.
Inventor： Giuseppe CALDERONI , Marco ATTANASIO
IPC: H02M3/158 , G09G3/3258 , H02M1/00
Abstract: A load is powered between positive and negative rails. A switching converter generates the negative rail voltage based on an input voltage, with a power transistor involved therein. A replica generator produces a replica voltage mirroring the drain-to-source voltage of the power transistor. A buffer buffers the replica voltage. A first switch selectively connects the buffered voltage to an output node, in response to a control signal with a duty-cycle proportional to the input voltage divided by the negative rail voltage. A second switch selectively connects the buffered voltage to ground, according to the inverse of the control signal, resulting in a PWM signal at the output node. An output filter filters the PWM signal to generate a sense voltage indicative of the output current flowing from the load device. A processing circuit determines the input current from the positive rail to the load device based on the sense voltage.
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公开(公告)号：US20250078925A1
公开(公告)日：2025-03-06
申请号：US18795936
申请日：2024-08-06
Applicant: STMicroelectronics International N.V
Inventor： Guillaume Docquier , Michael Nicolaes
IPC: G11C13/00
Abstract: The present description relates to a method of writing a first group of N data elements, N being an integer, into a second group of N memory cells of a phase-change memory, each data element of the first group comprising a metadata element, and at each writing of a data element of the first group into a memory cell of the second group, the value of the metadata element of the data element is modified.
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公开(公告)号：US20250078922A1
公开(公告)日：2025-03-06
申请号：US18241812
申请日：2023-09-01
Applicant: STMicroelectronics International N.V.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: A memory array includes memory cells arranged in a matrix with cell rows coupled to word lines and cell columns coupled to output bit lines. A control circuit maps a first group of memory cells to a first in-memory compute operation producing computation output signals on first output bit lines from a first matrix vector multiplication of a first input vector with a first group of computation weights stored in the first group of memory cells and maps a second group of memory cells to a second in-memory compute operation producing computation output signals on second output bit lines, different from the first output bit lines, from a second matrix vector multiplication of a second input vector, different from the first input vector, with a second group of computation weights stored in the second group of memory cells. The first and second in-memory compute operations are substantially simultaneously executed.
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公开(公告)号：US20250076048A1
公开(公告)日：2025-03-06
申请号：US18240955
申请日：2023-08-31
Applicant: STMicroelectronics International N.V.
Inventor： Alessandro MAGNANI , Matteo QUARTIROLI , Alessandro MECCHIA
IPC: G01C19/5712 , G01C25/00
Abstract: A sensor module includes a pattern generator configured to generate a variable frequency self-test signal. The sensor module includes an inertial sensor including a self-test electrode configured to receive the frequency sweep self-test signal. The inertial sensor is configured to generate an analog sensor signal based on the self-test signal. The sensor module includes an analog to digital converter configured to generate a digital sensor signal based on the analog sensor signal and a demodulator including a first input configured to receive the digital sensor signal, a second input configured to receive the self-test signal, and an output configured to output a demodulated signal. The sensor module includes a first low pass filter coupled to the output of the demodulator and configured to generate a baseband signal. The sensor module includes a calibration circuit configured to identify different MEMS characteristics, like resonance frequency, Q-factor, or sensitivity based on the baseband signal.
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公开(公告)号：US20250072787A1
公开(公告)日：2025-03-06
申请号：US18458879
申请日：2023-08-30
Inventor： Diego CARRERA , Carlo GHIGLIONE , Beatrice ROSSI , Pasqualina FRAGNETO , Giacomo BORACCHI
Abstract: A method of operating an inertial sensor module includes receiving a stream of inertial sensor data representing activity of a user of an electronic device and generating a plurality of wavelet sub-bands by performing a wavelet transform on the inertial sensor data. The method includes identifying a wavelet sub-band of highest energy from the plurality of wavelet sub-bands, generating augmented inertial sensor data by combining the wavelet sub-band of highest energy to the inertial sensor data, and identifying a first transition in the activity of the user based on the augmented inertial sensor data.
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