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公开(公告)号：US20210068739A1
公开(公告)日：2021-03-11
申请号：US17009503
申请日：2020-09-01
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Rundo , Sabrina Conoci , Concetto Spampinato
Abstract: An embodiment method comprises collecting at least one electrophysiological signal of a human over a limited time duration, and computing a set of electrophysiological signal features. The computing comprises at least one of: providing at least one reference electrophysiological signal and applying dynamic time warping processing to the at least one collected and at least one reference electrophysiological signals, applying stacked-auto-encoder artificial neural network processing to the collected electrophysiological signal, or filtering the electrophysiological signal collected via joint low-pass and high-pass filtering. The method further comprises applying pattern recognition processing to the computed set of features, producing a virtual key signal indicative of an identity of the human, and applying the virtual key signal to a user circuit to switch it between a first state and a second state as a result of the virtual key signal matching an authorized key signal stored in the user circuit.
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公开(公告)号：US10943896B2
公开(公告)日：2021-03-09
申请号：US15965759
申请日：2018-04-27
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Davide Giuseppe Patti
IPC: H01L27/02 , H01L29/10 , H01L29/78 , H01L29/417 , H01L29/66
Abstract: Power MOS device, in which a power MOS transistor has a drain terminal that is coupled to a power supply node, a gate terminal that is coupled to a drive node and a source terminal that is coupled to a load node. A detection MOS transistor has a drain terminal that is coupled to a detection node, a gate terminal that is coupled to the drive node and a source terminal that is coupled to the load node. A detection resistor has a first terminal coupled to the power supply node and a second terminal coupled to the detection node.
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公开(公告)号：US20210067157A1
公开(公告)日：2021-03-04
申请号：US16983596
申请日：2020-08-03
Applicant: STMicroelectronics S.r.l.
Inventor： Andrea Agnes
IPC: H03K17/687 , H03K17/16 , H02J7/00 , H02M3/158
Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.
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公开(公告)号：US20210050859A1
公开(公告)日：2021-02-18
申请号：US16993608
申请日：2020-08-14
Applicant: STMicroelectronics S.r.l.
Inventor： Giovanni SICURELLA , Manuela LA ROSA
Abstract: A multiple-input analog-to-digital converter device includes analog-to-digital converter circuits arranged between input nodes and output nodes. The analog-to-digital converter circuits operate over respective conversion times to provide simultaneous conversion of the analog input signals into respective conversion time signals. A time-to-digital converter circuit includes timer circuitry common to the plurality of analog-to-digital converter circuits. The timer circuitry cooperates with the analog-to-digital converter circuits to convert the conversion time signals into digital output signals at the output nodes.
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公开(公告)号：US10924194B2
公开(公告)日：2021-02-16
申请号：US16394633
申请日：2019-04-25
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Belfiore
Abstract: A radio-frequency transceiver device includes a transmission circuit generating a transmission signal at a transmission pad connected to a transmission antenna by modulating a radio frequency signal as a function of a control signal. First and second reception circuits receive first and second signals at first and second reception pads connected to first and second reception antennas. The received first and second signals are demodulated via the radio frequency signal to generate first and second demodulated reception signals. A control circuit operates during a reception test phase to generate only the control signal in order to test, as a function of the first and second demodulated reception signals, whether the received first signal corresponds to the received second signal. A reception error signal indicating a reception error is generated when the test indicates that the received first and second reception signals do not correspond.
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Patent Agency Ranking
公开(公告)号：US10917087B2
公开(公告)日：2021-02-09
申请号：US16719053
申请日：2019-12-18
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42 , G05F1/618 , G05F1/56 , H02J7/34
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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447.发明授权公开(公告)号：US10916622B2
公开(公告)日：2021-02-09
申请号：US16144168
申请日：2018-09-27
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Davide Giuseppe Patti , Giuseppina Valvo , DelfoNunziato Sanfilippo
IPC: H01L49/02 , H01L23/522
Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.
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公开(公告)号：US10914938B2
公开(公告)日：2021-02-09
申请号：US15955107
申请日：2018-04-17
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto Carminati , Sonia Costantini , Marta Carminati
Abstract: An oscillating structure includes first and second torsional elastic elements that define an axis of rotation and a moving element that is interposed between the first and second torsional elastic elements. The moving element, the first torsional elastic element and the second torsional elastic element lie in a first plane and are not in direct contact with one another. A coupling structure mechanically couples the moving element, the first torsional elastic element and the second torsional elastic element together. The moving element, the first torsional elastic element and the second torsional elastic element lie in a second plane different from the first plane. Oscillation of the moving element occurs as a result of a twisting of the first and second torsional elastic elements.
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449.发明授权公开(公告)号：US10914647B2
公开(公告)日：2021-02-09
申请号：US16023918
申请日：2018-06-29
Applicant: STMicroelectronics S.r.l.
Inventor： Francesco Pappalardo , Agatino Pennisi , Elio Guidetti , Angelo Doriani
Abstract: A capacitive sensor for monitoring stresses acting in a construction structure and having a multi-layer structure provided with an upper conductive layer defining an upper outer surface of the sensor. A lower conductive layer defines a lower outer surface. At least a first structural layer of insulating material is in contact with the upper conductive layer and at least a second structural layer of insulating material is in contact with the lower conductive layer. At least a first plate layer of conductive material and at least a second plate layer, of conductive material, and at least one dielectric layer is interposed between the first plate layer and the second plate layer to define at least one detection capacitor inside the multi-layer structure of the sensor. The upper and lower conductive layers jointly defining an electromagnetic screen for screening the detection capacitor against electromagnetic interference originating from outside the capacitive sensor.
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公开(公告)号：US10910302B2
公开(公告)日：2021-02-02
申请号：US16385928
申请日：2019-04-16
Applicant: STMicroelectronics S.r.l.
Inventor： Cristiano Gianluca Stella , Agatino Minotti
IPC: H01L23/498 , H01L23/373
Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
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