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公开(公告)号：US10892234B2
公开(公告)日：2021-01-12
申请号：US16154456
申请日：2018-10-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Abderrezak Marzaki
Abstract: An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.
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公开(公告)号：US10863018B2
公开(公告)日：2020-12-08
申请号：US16774954
申请日：2020-01-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pierre Demaj , Laurent Folliot
IPC: H04M1/725 , G01D21/02 , H04W4/02 , H04W12/00 , H04W4/029 , H04W52/02 , G06F9/445 , G06F3/01 , G06K9/00 , H04W4/38 , H04W56/00 , H04W4/33 , H04W4/23
Abstract: A method of real-time scene detection performed by a wireless communication device includes, performing a first scene detection measurement to determine that the wireless communication device is located in a first scene. The first scene detection measurement is performed at first instant in time. The first scene is a type of environment. The method further includes associating the first scene with a corresponding reference scene of a predetermined set of reference scenes, determining a reference duration associated with the corresponding reference scene, and performing a second scene detection measurement immediately following expiration of the reference duration measured from the first instant in time.
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公开(公告)号：US10862396B2
公开(公告)日：2020-12-08
申请号：US16599450
申请日：2019-10-11
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Sebastien Ortet , Didier Davino , Cedric Thomas
Abstract: An electronic device includes a switched-mode power supply having a first operating phase during which the output node of the switched-mode power supply is coupled by an on switch to a source of a first reference voltage. The first operating phase is followed by a second operation phase during which the output node of the switched-mode power supply is in a high impedance state. While in the second operating phase, a capacitor connected to the output node of the switched-mode power supply at least partially discharges into a load.
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公开(公告)号：US20200373295A1
公开(公告)日：2020-11-26
申请号：US16877935
申请日：2020-05-19
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francois TAILLIET
Abstract: A first power supply rail is provided as a power supply tree configured with couplings to distribute a supply voltage to active elements of the circuit. A second power supply rail is provided as an electrostatic discharge channel and is not configured with distribution tree couplings to active elements of the circuit. A first electrostatic discharge circuit is directly electrically connected between one end of the second power supply rail and a ground rail. A second electrostatic discharge circuit is directly electrically connected between an interconnect node and the ground rail. The interconnect node electrically interconnects another end of the second power supply rail to the first power supply rail at the second electrostatic discharge circuit.
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公开(公告)号：US20200313846A1
公开(公告)日：2020-10-01
申请号：US16810434
申请日：2020-03-05
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Ibrahima DIOP , Yanis LINGE
Abstract: Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.
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Patent Agency Ranking
公开(公告)号：US20200310805A1
公开(公告)日：2020-10-01
申请号：US16833012
申请日：2020-03-27
Inventor： Michael PEETERS , Fabrice MARINET
Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
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公开(公告)号：US20200303423A1
公开(公告)日：2020-09-24
申请号：US16898700
申请日：2020-06-11
Inventor： Jean-Jacques FAGOT , Philippe BOIVIN , Franck ARNAUD
IPC: H01L27/12 , H01L21/84 , H01L21/762
Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
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公开(公告)号：US20200302266A1
公开(公告)日：2020-09-24
申请号：US16810582
申请日：2020-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pierre Demaj , Laurent Folliot
IPC: G06N3/04
Abstract: In accordance with an embodiment, a method includes reducing a size of at least one initial parameter of each layer of an initial multilayer neural network to obtain for each layer a set of new parameters defining a new neural network, wherein each new parameter of the set of new parameters has its data represented in two portions comprising an integer portion and a fractional portion; implementing the new neural network using a test input data set applied only once to each layer; determining a distribution function or a density function resulting from the set of new parameters for each layer; and based on the determined distribution function or density function, adjusting a size of a memory area allocated to the fractional portion and a size of the memory area allocated to the integer portion of each new parameter associated with each layer.
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公开(公告)号：US10783091B2
公开(公告)日：2020-09-22
申请号：US16130858
申请日：2018-09-13
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Fabrice Romain
Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.
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公开(公告)号：US10769513B2
公开(公告)日：2020-09-08
申请号：US16227525
申请日：2018-12-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Alexandre Sarafianos , Thomas Ordas , Yanis Linge , Jimmy Fort
IPC: G06K19/073 , G06F21/75 , G06F21/44 , H01L23/00
Abstract: An electronic device includes a logic circuit and an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal intended coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.
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