公开(公告)号：US20210295585A1

公开(公告)日：2021-09-23

申请号：US16825600

申请日：2020-03-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Saad ARRABI ,  Vishrut VAIBHAV ,  Mangesh P. NIJASURE ,  Todd MARTIN

IPC: G06T15/00

Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.

公开(公告)号：US20210287418A1

公开(公告)日：2021-09-16

申请号：US17008292

申请日：2020-08-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. ACHARYA ,  Ruijin WU ,  Young In YEO ,  Mika TUOMI ,  Kiia KALLIO

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06F7/24

Abstract: A processor dynamically selects a render mode for each render pass of a frame based on the characteristics of the render pass. A software driver of the processor receives graphics operations from an application executing at the processor and converts the graphics operations into a command stream that is provided to the graphics pipeline. As the driver converts the graphics operations into the command stream, the driver analyzes each render pass of the frame to determine characteristics of the render passes, and selects a render mode for each render pass based on the characteristics of the render pass.

公开(公告)号：US20210287325A1

公开(公告)日：2021-09-16

申请号：US17182952

申请日：2021-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Lou Isabelle Kramer ,  Matthäus G. Chajdas

IPC: G06T1/20 ,  G06T3/40 ,  G06F9/48

Abstract: Systems, apparatuses, and methods for implementing a downsampler in a single compute shader pass are disclosed. A central processing unit (CPU) issues a single-pass compute shader kernel to perform downsampling of a texture on a graphics processing unit (GPU). The GPU includes a plurality of compute units for executing thread groups of the kernel. Each thread group fetches a patch of the texture, and each individual thread downsamples four quads of texels to compute mip levels 1 and 2 independently of the other threads. For mip level 3, texel data is written back over one of the local data share (LDS) entries from which the texel data was loaded. This eliminates the need for a barrier between loads and stores for computing mip level 3. The remaining mip levels are computed in a similar fashion by the thread groups of the single-pass kernel.

公开(公告)号：US11120190B2

公开(公告)日：2021-09-14

申请号：US15819879

申请日：2017-11-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/528 ,  G06F30/39 ,  G06F30/394 ,  G06F30/398 ,  G06F119/06 ,  G06F119/18

Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.

公开(公告)号：US11112926B1

公开(公告)日：2021-09-07

申请号：US17085597

申请日：2020-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Peter James Lohrmann

IPC: G06F3/048 ,  G06T3/40

Abstract: Systems, apparatuses, and methods for implementing enhanced scaling techniques for display objects are disclosed. When graphical content is created by an application, display objects register with a scaling manager to be notified of display scaling events. These display scaling events can be caused by changing displays, changing resolution or other parameters on a display, changing a text size, resizing one or more graphical elements, or otherwise. When a display scaling event is detected, display objects are notified of the event by the scaling manager. If a given display object makes a decision to change the amount of space it occupies based on the event, the given display object notifies its parent object of the desired change. The parent can then decide whether to allow the change and/or to make adjustments to other display objects to accommodate the change sought by the given display object.

公开(公告)号：US20210272229A1

公开(公告)日：2021-09-02

申请号：US16804345

申请日：2020-02-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon MCCRARY

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus such as a graphics processing unit (GPU) includes shader engines and front end (FE) circuits. Subsets of the FE circuits are configured to schedule commands for execution on corresponding subsets of the shader engines. The apparatus also includes a set of physical paths configured to convey information from the FE circuits to a memory via the shader engines. Subsets of the physical paths are allocated to the subsets of the FE circuits and the corresponding subsets of the shader engines. The apparatus further includes a scheduler configured to receive a reconfiguration request and modify the set of physical paths based on the reconfiguration request. In some cases, the reconfiguration request is provided by a central processing unit (CPU) that requests the modification based on characteristics of applications generating the commands.

公开(公告)号：US11106596B2

公开(公告)日：2021-08-31

申请号：US15389955

申请日：2016-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John M. King ,  Michael T. Clark

IPC: G06F12/1027 ,  G06F12/123 ,  G06F12/127

Abstract: Methods, devices, and systems for determining an address in a physical memory which corresponds to a virtual address using a skewed-associative translation lookaside buffer (TLB) are described. A virtual address and a configuration indication are received using receiver circuitry. A physical address corresponding to the virtual address is output if a TLB hit occurs. A first subset of a plurality of ways of the TLB is configured to hold a first page size. The first subset includes a number of the ways based on the configuration indication. A physical address corresponding to the virtual address is retrieved from a page table if a TLB miss occurs, and at least a portion of the physical address is installed in a least recently used way of a subset of a plurality of ways the TLB, determined according to a replacement policy based on the configuration indication.

公开(公告)号：US11100604B2

公开(公告)日：2021-08-24

申请号：US16263709

申请日：2019-01-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Jeffrey Gongxian Cheng ,  Ahmed M. Abdelkhalek ,  Yinan Jiang ,  Xingsheng Wan ,  Anthony Asaro ,  David Martinez Nieto

IPC: G06F15/80 ,  G06T1/20 ,  G06F9/38 ,  G06F9/48 ,  G06T15/00

Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.

公开(公告)号：US11068458B2

公开(公告)日：2021-07-20

申请号：US16202082

申请日：2018-11-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mohamed Assem Ibrahim ,  Onur Kayiran ,  Yasuko Eckert

IPC: G06F16/22 ,  G06F16/901

Abstract: A portion of a graph dataset is generated for each computing node in a distributed computing system by, for each subject vertex in a graph, recording for the computing node an offset for the subject vertex, where the offset references a first position in an edge array for the computing node, and for each edge of a set of edges coupled with the subject vertex in the graph, calculating an edge value for the edge based on a connected vertex identifier identifying a vertex coupled with the subject vertex via the edge. When the edge value is assigned to the first position, the edge value is determined by a first calculation, and when the edge value is assigned to position subsequent to the first position, the edge value is determined by a second calculation. In the computing node, the edge value is recorded in the edge array.

公开(公告)号：US11064019B2

公开(公告)日：2021-07-13

申请号：US15265402

申请日：2016-09-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov

IPC: H04L29/08 ,  H04L12/24 ,  H04L12/725 ,  H04L12/927

Abstract: A server includes a plurality of nodes that are connected by a network that includes an on-chip network or an inter-chip network that connects the nodes. The server also includes a controller to configure the network based on relative priorities of workloads that are executing on the nodes. Configuring the network can include allocating buffers to virtual channels supported by the network based on the relative priorities of the workloads associated with the virtual channels, configuring routing tables that route the packets over the network based on the relative priorities of the workloads that generate the packets, or modifying arbitration weights to favor granting access to the virtual channels to packets generated by higher priority workloads.