Triple modular redundancy (TMR) radiation hardened memory system

    公开(公告)号:US11861181B1

    公开(公告)日:2024-01-02

    申请号:US17818850

    申请日:2022-08-10

    Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

    FAST FOURIER TRANSFORM (FFT) SAMPLE REORDER CIRCUIT FOR A DYNAMICALLY RECONFIGURABLE OVERSAMPLED CHANNELIZER

    公开(公告)号:US20230421425A1

    公开(公告)日:2023-12-28

    申请号:US17847896

    申请日:2022-06-23

    CPC classification number: H04L27/2651 G06F17/142

    Abstract: Techniques are provided for a fast Fourier transform (FFT) sample reorder circuit for a dynamically reconfigurable oversampled channelizer. An FFT sample reorder circuit implementing the techniques according to an embodiment includes a plurality of dual port memory circuits. The circuit also includes a first crossbar circuit configured to route input data samples to write ports of the plurality of dual port memory circuits. The circuit further includes a second crossbar circuit configured to route reordered output data samples from read ports of the plurality of dual port memory circuits to a multi-stage FFT circuit. The circuit further includes a controller circuit configured to control the routing of the input data samples and the routing of the reordered output data samples based on a selection of a stage of the multi-stage FFT circuit.

    POLYPHASE FILTER FOR A DYNAMICALLY RECONFIGURABLE OVERSAMPLED CHANNELIZER

    公开(公告)号:US20230421137A1

    公开(公告)日:2023-12-28

    申请号:US17847892

    申请日:2022-06-23

    CPC classification number: H03H17/0227 G06F7/523 G06F7/50

    Abstract: Techniques are provided for a polyphase filtering in a dynamically reconfigurable two times (2×) oversampled channelizer. A polyphase filter implementing the techniques according to an embodiment includes a first plurality of dual port memory circuits and a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits. The polyphase filter also includes a second plurality of dual port memory circuits configured to store polyphase filter coefficients and a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. The polyphase filter further includes a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients and an adder circuit to sum the results of the multiplications to generate a filtered output.

    DYNAMICALLY RECONFIGURABLE OVERSAMPLED CHANNELIZER

    公开(公告)号:US20230418898A1

    公开(公告)日:2023-12-28

    申请号:US17847887

    申请日:2022-06-23

    CPC classification number: G06F17/142 H04B1/18 H04L25/03828 H03H17/0223

    Abstract: Techniques are provided for a dynamically reconfigurable two times (2×) oversampled channelizer. A channelizer implementing the techniques according to an embodiment includes a polyphase filter, a two phase reorder circuit, a fast Fourier transform (FFT) circuit, and a two phase merge circuit. The polyphase filter is configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output. The two phase reorder circuit is configured to split a 2× oversampled data stream into two parallel, critically sampled data streams. The FFT circuit is configured to transform each stream into the frequency domain. The two phase merge circuit is configured to merge the two streams of frequency domain data into a single stream of 2× oversampled frequency domain data for distribution onto frames of frequency bins. Reconfigurable parameters for the channelizer include filter coefficients, number of filter folds, and number of frequency bins.

    MULTI-FREQUENCY SAMPLING SYSTEM
    50.
    发明公开

    公开(公告)号:US20230336194A1

    公开(公告)日:2023-10-19

    申请号:US17659554

    申请日:2022-04-18

    CPC classification number: H04B1/0078 H04B1/588 H04B1/0042

    Abstract: Techniques are provided for a multi-frequency sampling system. A system implementing the techniques according to an embodiment includes a first bandpass filter to filter a radio frequency (RF) signal to generate a first filtered signal in a first frequency band, and a second bandpass filter to filter the RF signal to generate a second filtered signal in a second frequency band. The system also includes a first analog to digital converter (ADC) operating at a first sampling frequency to convert the first filtered signal to a first digital signal and a second ADC operating at a second sampling frequency to convert the second filtered signal to a second digital signal. The first frequency band is selected to avoid a first Nyquist boundary zone associated with the first sampling frequency and the second frequency band is selected to avoid a second Nyquist boundary zone associated with the second sampling frequency.

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