Abstract:
A gate driving circuit includes a plurality of stages which are connected to each other one after another and each stage of the plurality of stages outputs a gate voltage to a corresponding gate line of a plurality of gate lines in response to at least one clock signal. Each stage of the plurality of stages includes; a voltage output part which outputs the gate voltage, an output driving part which drives the voltage output part, a holding part which holds the gate line at an off-voltage, and a discharge part arranged at a first end of the gate line to discharge the gate line to the off-voltage in response to the gate voltage output from the voltage output part.
Abstract:
A liquid crystal display (LCD) includes a substrate; first and second pixel rows formed on the substrate and including a plurality of pixels; a first gate line extending in a row direction on the substrate and connected with the first pixel row; a second gate line extending in the row direction on the substrate, connected with the first pixel row; a third gate line extending in the row direction on the substrate, connected with the second pixel row, and adjacent to the second gate line; a fourth gate line extending in the row direction on the substrate, connected with the second pixel row; a plurality of data lines extending in a column direction on the substrate, wherein each of the data lines are disposed every two of the pixels; a first gate driver connected with the first and fourth gate lines and applying gate signals to the first and fourth gate lines; and a second gate driver connected with the second and third gate lines and applying gate signals to the second and third gate lines.
Abstract:
A display substrate includes a base substrate, a first line, a second line, a bridge line, a thin-film transistor (TFT), a storage line, and a pixel electrode. The first line extends in a first direction on the base substrate. The second line extends in a second direction on the base substrate and is divided into two portions with respect to the first line. The bridge line makes contact with the two portions of the second line in first and second bridge contact regions. The TFT includes a source electrode making contact with one of the first and second lines in a data contact region. The storage line is formed on the one of the first and second lines. The pixel electrode is formed on the storage line and is electrically connected to the TFT. The display substrate reduces formation of parasitic capacitance between pixel electrode and data line.
Abstract:
A display substrate includes a first switching element, a second switching element, a first pixel electrode, a second pixel electrode, a main storage electrode and a sub-storage electrode. The first switching element is connected to a data line and a first gate line. The second switching element is connected to the data line and a second gate line adjacent to the first gate line. The first pixel electrode is electrically connected to the first switching element. The second pixel electrode is electrically connected to the second switching element. The main storage electrode is disposed in an area between the first pixel electrode and the second electrode to overlap with first ends of the first and second pixel electrodes. The sub-storage electrode is spaced apart from the first and second gate lines.
Abstract:
A gate driving circuit and a display apparatus having the gate driving circuit include a pull-up part and a carry part pull up a present gate signal and a present carry signal, respectively, to a first clock during a first period within one frame. A pull-down part receives a next gate signal to discharge the present gate signal to a source power voltage. A pull-up driving part is connected to control terminals of the carry part and pull-up part (Q-node) to turn the carry part and pull-up part on and off. A floating preventing part prevents an output terminal of the carry part from being floated in response to the first clock during a second period within the one frame.
Abstract:
A display apparatus includes a thin film transistor array panel including a display region and a non-display region, a gate line extending along a first direction, a data line extending along a second direction, substantially perpendicular to the first direction, the data line being insulated from and crossing the gate line, a storage electrode line which receives a common voltage signal, and a first gate driver disposed on the thin film transistor array panel and which supplies at least one of a gate on signal and a gate off signal to the gate line. The storage electrode line includes a first portion extending along the first direction and a second portion extending along the second direction in the non-display region. A width, measured along the second direction, of the first portion is less than a width, measured along the first direction, of the second portion.
Abstract:
A display substrate includes a first metal pattern formed on a substrate and includes a data line to which a pixel voltage is applied, an insulating layer formed on the substrate on which the first metal pattern is formed, an active pattern formed on the insulating layer, a second metal pattern formed on the insulating layer and including a gate line and a storage line, the gate line crossing the data line, a scanning signal applied to the gate line, a protective layer formed on the substrate on which the second metal pattern is formed, and a pixel electrode formed on the protective layer. A method for manufacturing the display substrate, and a display apparatus including the display substrate are further provided.
Abstract:
In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n−1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n−1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.
Abstract:
A scan driver sequentially activates scan lines of a display apparatus having m-number of scan lines. The scan driver includes a pull-up driving section and a pull-down driving section. The pull-up driving section includes a pull-up transistor that is electrically connected to an ith scan line to activate the ith scan line to be in a high level state. The pull-down driving section includes a pull-down transistor that is electrically connected to the ith scan line to inactivate the ith scan line to be in a low level state when (i+1)th scan line is activated. A gate electrode of the pull-up transistor is electrically separated from the ith scan line. The above ‘m’ is an integer greater than 1, and ‘i’ is an integer no greater than ‘m’. Therefore, display defects may be minimized, and detecting a cause of the display defect may be simplified to enhance productivity.
Abstract:
A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having an output terminal electrically connected to a respective one of the plurality of gate lines. The multiple signal applying unit applies a sub scan signal and a main scan signal. The sub scan signal and the main scan signal sequentially activate each of the plurality of gate lines. Therefore, the scan lines receive the scan signal twice, so that the liquid crystal capacitors electrically connected to the gate lines receive the data voltage twice. As a result, even though the time for charging the liquid crystal capacitors may be reduced, the liquid crystal capacitors may be fully charged to enhance display quality.