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41.发明申请System and Method for Completing Full Updates to Entire Cache Lines Stores with Address-Only Bus Operations 有权完整的完整更新的系统和方法完整的缓存行存储仅地址总线操作公开(公告)号：US20080140943A1
公开(公告)日：2008-06-12
申请号：US12034769
申请日：2008-02-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译： 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失或数据在RC写入权限获得之前状态时，不会检索高速缓存行的数据。
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42.发明申请Method for Priority Scheduling and Priority Dispatching of Store Conditional Operations in a Store Queue 有权存储队列中存储条件操作优先级调度和优先调度的方法公开(公告)号：US20080140936A1
公开(公告)日：2008-06-12
申请号：US12033441
申请日：2008-02-19
IPC分类号： G06F12/08
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.
摘要翻译： 一种方法，系统和处理器芯片设计，用于减少完成LARX操作和接收相关联的STCX操作之间的延迟，以完成对高速缓存行的更新。 向发行处理器的存储队列的每个条目提供附加跟踪位（优先级位）。 每当在条目中放置STCX操作时，优先级位置位。 在选择由仲裁逻辑发送的条目期间，仲裁逻辑扫描每个合格条目的优先级位的值。 具有优先级位的条目在架构规则中的选择过程中被赋予优先级。 然后在既定规则内尽可能早地选择该条目进行发送。
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43.发明授权Processor, method, and data processing system employing a variable store gather window 有权处理器，方法和数据处理系统采用变量存储收集窗口公开(公告)号：US07366851B2
公开(公告)日：2008-04-29
申请号：US10922272
申请日：2004-08-19
IPC分类号： G06F12/08
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。
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44.发明授权Data processing system and method for efficient L3 cache directory management 有权数据处理系统和方法，用于高效的L3缓存目录管理公开(公告)号：US07337280B2
公开(公告)日：2008-02-26
申请号：US11055301
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/128 , G06F2212/2542
摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。
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45.发明授权Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database 失效通过参考可逆配置数据库来确定数字设计的配置的方法，系统和程序产品公开(公告)号：US07266489B2
公开(公告)日：2007-09-04
申请号：US10425053
申请日：2003-04-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , Y10S707/99945 , Y10S707/99948
摘要： A method for determining the configuration of a digital design first obtains a set of latch values of a plurality of latches within the digital design. A setting of a Dial instance is then determined based upon the set of latch values by reference to a configuration database that specifies a mapping table uniquely associating each a plurality of different settings of the Dial with a respective one of a plurality of different sets of latch values. The setting of the Dial instance is then output. In one embodiment, the setting of the Dial is contained in a simulation setup file utilized to configure a simulation model to a state approximating the state of the digital design represented by the set of latch values.
摘要翻译： 用于确定数字设计的配置的方法首先获得数字设计内的多个锁存器的一组锁存值。 然后，通过参考配置数据库，基于锁定值的集合来确定Dial实例的设置，该配置数据库指定将Dial的多个不同设置中的每一个与多个不同组的锁存器中的相应一个独立地相关联的映射表 价值观。 然后输出拨号实例的设置。 在一个实施例中，Dial的设置包含在用于将仿真模型配置为接近由锁定值组表示的数字设计的状态的状态的模拟设置文件中。
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46.发明授权Method, system and program product providing a configuration specification language having split latch support 有权提供具有分离锁存器支持的配置规范语言的方法，系统和程序产品公开(公告)号：US07249330B2
公开(公告)日：2007-07-24
申请号：US10749581
申请日：2003-12-31
CPC分类号： G06F17/5022
摘要： Methods, data processing systems, and program products supporting multi-cycle simulation are disclosed. According to one method, a configuration database including at least one data structure representing an instance of a Dial entity is received. The instance of the Dial entity has at least an input, an output, and at least one associated latch within a digital design. A value of the output of the instance of the Dial entity controls a value stored within the associated latch. A control file is also received. The control file indicates that at least one associated latch data structure is to be inserted within the configuration database to represent the latch during multi-cycle simulation. In response to receipt of the configuration database and the control file, the configuration database is processed with reference to the control file to insert within the configuration database at least one latch data structure and to associate, within the configuration database, the at least one latch data structure with the instance of the Dial entity.
摘要翻译： 公开了支持多循环模拟的方法，数据处理系统和程序产品。 根据一种方法，接收包括表示Dial实体的实例的至少一个数据结构的配置数据库。 Dial实体的实例在数字设计中至少具有输入，输出和至少一个相关联的锁存器。 Dial实例的实例的输出值控制存储在相关联的锁存器内的值。 还收到一个控制文件。 控制文件指示在多循环模拟期间，至少一个相关联的锁存数据结构将被插入配置数据库中以表示锁存器。 响应于接收到配置数据库和控制文件，参考控制文件来处理配置数据库，以在配置数据库内插入至少一个锁存数据结构，并且在配置数据库内将至少一个锁存器 数据结构与Dial实体的实例。
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47.发明授权Processor, data processing system and method for synchronizing access to data in shared memory 失效处理器，数据处理系统和方法，用于同步共享存储器中数据的访问公开(公告)号：US07200717B2
公开(公告)日：2007-04-03
申请号：US10965144
申请日：2004-10-14
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/3851 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.
摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元， 同时执行多个指令线程。 所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令 如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。
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48.发明授权Method and system for reducing storage and transmission requirements for simulation results 失效减少模拟结果存储和传输要求的方法和系统公开(公告)号：US07194400B2
公开(公告)日：2007-03-20
申请号：US10355684
申请日：2003-01-30
CPC分类号： G06F17/5022
摘要： A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.
摘要翻译： 模拟控制程序接收包括设计实体和计数事件寄存器的硬件描述语言（HDL）模型。 每个计数事件寄存器与事件的相应实例相关联。 计数事件寄存器包括第一和第二寄存器，用于计数在HDL模型内具有相同分层级别的相同设计实体的不同实例内生成的相同复制事件的发生。 仿真控制程序还接收指示哪些计数事件寄存器与相同复制事件的实例相关联的相关数据结构。 在仿真处理期间，每个计数事件寄存器维持表示相关事件实例发生次数的相应计数值。 仿真控制程序根据相关数据结构对第一和第二计数事件寄存器的计数值求和，并输出包含累计计数值的计数事件数据包。
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49.发明授权Method, system and program product that utilize a configuration database to configure a hardware digital system having an arbitrary system size and component set 失效使用配置数据库来配置具有任意系统大小和组件集的硬件数字系统的方法，系统和程序产品公开(公告)号：US07146302B2
公开(公告)日：2006-12-05
申请号：US10425076
申请日：2003-04-28
CPC分类号： G06F17/5045
摘要： A system configuration database is constructed in volatile memory by first determining which types of integrated circuits are present in a hardware system and the number of each type. In response to a determination, a system configuration database is loaded into volatile memory that includes a respective chip hardware database for each type of integrated circuit in the hardware system. Each chip hardware database defines a Dial entity controlling which of a plurality of different possible latch values is placed in a hardware latch of the associated type of integrated circuit. The system configuration database includes at least a first chip hardware database for a first type of integrated circuit that contains per-instance information for each of the multiple instances of the first type of integrated circuit within the hardware system.
摘要翻译： 通过首先确定在硬件系统中存在哪种类型的集成电路和每种类型的数量，在易失性存储器中构造系统配置数据库。 响应于确定，将系统配置数据库加载到易失性存储器中，其包括用于硬件系统中的每种类型的集成电路的相应芯片硬件数据库。 每个芯片硬件数据库定义了一个Dial实体，其控制多个不同可能的锁存值中的哪一个被放置在相关类型的集成电路的硬件锁存器中。 系统配置数据库至少包括用于第一类型集成电路的第一芯片硬件数据库，其包含硬件系统内的第一类型集成电路的多个实例中的每个实例信息。
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50.发明授权System and method to stall dispatch of gathered store operations in a store queue using a timer 失效使用定时器将存储队列中收集的存储操作分派的系统和方法停止公开(公告)号：US07089364B2
公开(公告)日：2006-08-08
申请号：US10825188
申请日：2004-04-15
IPC分类号： G06F12/12
CPC分类号： G06F12/0897 , G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F12/0804
摘要： A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.
摘要翻译： 一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。 为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。 当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。 通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。 当某些条件发生时，该条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器饱和。 计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。
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