利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

217 条记录 (耗时 0.054 秒)

    Data processing system and method for efficient L3 cache directory management
    1.
    发明授权
    Data processing system and method for efficient L3 cache directory management 有权
    数据处理系统和方法，用于高效的L3缓存目录管理

    公开(公告)号：US07500065B2

    公开(公告)日：2009-03-03

    申请号：US11956102

    申请日：2007-12-13

    申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

    发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

    摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

    摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

    Data processing system and method for efficient L3 cache directory management
    2.
    发明授权
    Data processing system and method for efficient L3 cache directory management 有权
    数据处理系统和方法，用于高效的L3缓存目录管理

    公开(公告)号：US07337280B2

    公开(公告)日：2008-02-26

    申请号：US11055301

    申请日：2005-02-10

    申请人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

    发明人： Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Philip G. Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

    摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

    摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

    Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
    5.
    发明授权
    Data processing system and method for efficient communication utilizing an Tn and Ten coherency states 有权
    数据处理系统和利用Tn和10相​​关性状态的高效通信方法

    公开(公告)号：US07480772B2

    公开(公告)日：2009-01-20

    申请号：US11835984

    申请日：2007-08-08

    申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

    发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

    摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

    摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

    Processor, data processing system and method for synchronzing access to data in shared memory
    6.
    发明授权
    Processor, data processing system and method for synchronzing access to data in shared memory 失效
    处理器，数据处理系统和方法，用于同步共享存储器中数据的访问

    公开(公告)号：US07197604B2

    公开(公告)日：2007-03-27

    申请号：US10965151

    申请日：2004-10-14

    申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

    摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

    摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。

    Processor, data processing system and method for synchronizing access to data in shared memory
    8.
    发明授权
    Processor, data processing system and method for synchronizing access to data in shared memory 失效
    处理器，数据处理系统和方法，用于同步共享存储器中数据的访问

    公开(公告)号：US07200717B2

    公开(公告)日：2007-04-03

    申请号：US10965144

    申请日：2004-10-14

    申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0811 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3851 ,  G06F12/0855

    摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit coupled to the instruction sequencing unit that concurrently executes multiple threads of instructions. The processor core, responsive to the at least one instruction execution unit executing a load-reserve instruction in a first thread that binds to a load target address in the store-through upper level cache during a reservation hazard window associated with a conflicting store-conditional operation of a second thread, causes a subsequent store-conditional operation of the first thread to a store target address matching the load target address to fail if the store-conditional operation of the second thread succeeds.

    摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括处理器核心，该处理器核心包括通过存储的上级高速缓存，指令执行指令排序单元，数据寄存器以及耦合到指令排序单元的至少一个指令执行单元， 同时执行多个指令线程。 所述处理器核心响应于所述至少一个指令执行单元在与冲突存储条件相关联的预留危险窗口期间执行在所述存储通过上级高速缓存中的绑定到加载目标地址的第一线程中的加载保留指令 如果第二线程的存储条件操作成功，则第二线程的操作使得第一线程的后续存储条件操作到与加载目标地址匹配的存储目标地址失败。

    Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing
    9.
    发明授权
    Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing 失效
    减少缓存子系统中的布线拥塞，利用具有不连续寻址的扇区缓存

    公开(公告)号：US08433851B2

    公开(公告)日：2013-04-30

    申请号：US11839663

    申请日：2007-08-16

    申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

    发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams ,  Phillip G. Williams

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F12/0851 ,  G06F12/0864

    摘要： A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced-wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.

    摘要翻译： 一种方法和计算机系统，用于通过重新配置扇区到片分配和较低的高速缓存寻址方案来减少具有扇区和分片的低级高速缓存的高速缓存子系统中的布线拥塞，所需的房地产和访问延迟。 通过这种分配，具有不连续地址的扇区被放置在相同的片内，并且基于对高速缓存片内的可寻址扇区的这种重新分配，可以在两级低级高速缓存之间进行简化布线方案。 此外，低速缓存有效地址标签被重新配置，使得先前分配用于识别扇区和片的地址字段相对于地址标签内的彼此的位置被切换。 地址位的这种重新分配使得能够基于指示的扇区进行直接片寻址。