公开(公告)号：US06901005B2

公开(公告)日：2005-05-31

申请号：US10649752

申请日：2003-08-27

Applicant: Frederick A. Perner ,  Kenneth K. Smith

Inventor： Frederick A. Perner ,  Kenneth K. Smith

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/22

CPC classification number: G11C11/15

Abstract: Methods and apparatuses are disclosed for reducing the read time of a memory array. In one embodiment, the method includes sampling unknown data values from a plurality of memory elements, buffering the unknown values, writing known values to the plurality of memory elements and sampling the known values, and comparing the known values to the buffered values.

Abstract translation: 公开了用于减少存储器阵列的读取时间的方法和装置。 在一个实施例中，该方法包括从多个存储器元件采样未知数据值，缓冲未知值，将已知值写入多个存储器元件并对已知值进行采样，以及将已知值与缓冲值进行比较。

公开(公告)号：US06865107B2

公开(公告)日：2005-03-08

申请号：US10601895

申请日：2003-06-23

Applicant: Thomas C. Anthony ,  Frederick A. Perner ,  Manoj K. Bhattacharyya

Inventor： Thomas C. Anthony ,  Frederick A. Perner ,  Manoj K. Bhattacharyya

IPC: G11C11/15 ,  G11C11/14

CPC classification number: G11C11/15

Abstract: A magnetic memory array is described having a plurality of bit cells. Each bit cell includes at least one magnetic layer having free magnetic poles with a corresponding demagnetization field. A magnetic flux absorbing layer is disposed between at least two of the plurality of bit cells.

Abstract translation: 描述了具有多个位单元的磁存储器阵列。 每个位单元包括至少一个具有相应去磁场的具有自由磁极的磁性层。 磁通量吸收层设置在多个位单元中的至少两个位单元之间。

公开(公告)号：US06587384B2

公开(公告)日：2003-07-01

申请号：US09839012

申请日：2001-04-21

Applicant: Frederick A Perner

Inventor： Frederick A Perner

IPC: G11C700

CPC classification number: G11C11/16

Abstract: An input/output (I/O) circuit of a memory device performs I/O and stores data for write-backs. The write-back data may be used for destructive read operations. The I/O circuit may also be configured to perform data balancing, write-verifies and built-in self test (BIST).

公开(公告)号：US06580454B1

公开(公告)日：2003-06-17

申请号：US09195588

申请日：1998-11-18

Applicant: Frederick A. Perner ,  Charles M. C. Tan

Inventor： Frederick A. Perner ,  Charles M. C. Tan

IPC: H04N314

CPC classification number: H04N5/3535 ,  H01L27/14643 ,  H04N5/35509 ,  H04N5/37455

Abstract: A system and a method for imaging a scene of interest utilize variable exposure periods that have durations based upon detecting a fixed voltage drop in order to determine the scene segment radiance. The rate of voltage drop corresponds to the degree of scene segment radiance, such that high radiant scene segments yield faster voltage drops than lower radiant scene segments. The variable exposure period is determined within each pixel in a pixel array of the system to gather exposure periods from different segments of the scene being imaged. The measured exposure periods are translated into grayscale information that can be used to generate a composite image having various levels of grayscale that is representative of the imaged scene. Each pixel includes a photo sensor, an analog-to-digital converter and a memory to measure, digitize and store the exposure period. The memory contains a number of memory cells having a three-transistor configuration that are each connected to a bi-directional bit line. The bi-directional bit line functions as both a read bit line and a write bit line. The three-transistor configuration allows for non-destructive read-outs of data stored in the memory cells.

Abstract translation: 用于对感兴趣场景进行成像的系统和方法利用具有基于检测固定电压降的持续时间的可变曝光周期，以便确定场景段辐射度。 电压降的速率对应于场景段辐射度，使得高辐射场景段比较低的辐射场景段产生更快的电压降。 在系统的像素阵列中的每个像素内确定可变曝光周期，以从被成像的场景的不同片段收集曝光周期。 测量的曝光周期被转换成灰度信息，其可用于生成具有代表成像场景的各种灰度等级的合成图像。 每个像素包括光传感器，模数转换器和用于测量，数字化和存储曝光周期的存储器。 存储器包含多个具有三晶体管配置的存储单元，每个存储单元都连接到双向位线。 双向位线用作读位线和写位线。 三晶体管配置允许存储在存储器单元中的数据的非破坏性读出。

公开(公告)号：US06552745B1

公开(公告)日：2003-04-22

申请号：US09057429

申请日：1998-04-08

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: H04N314

CPC classification number: H04N5/37455

Abstract: An imaging apparatus and a method of capturing and storing an image in digital form within a photosensitive area of the apparatus include integrating an array of memory cells within each pixel of the photosensitive area. Preferably, the memory cells are dual port memory cells, such that write operations can be performed in a parallel manner while reading operations are performed in a serial manner. In the preferred embodiment, each array contains a sufficient number of memory cells to store two digital words representing a photo signal and a reference signal. A comparator within each pixel operating in unison with a counter and a ramp generator captures the photo signal and the reference signal in digital form. The design of the imaging apparatus allows each pixel in the photosensitive area to capture and store the signals in a parallel manner. The parallel function of the apparatus increases the electronic shutter speed, while the integrated memory array eliminates the need for an external frame buffer memory.

Abstract translation: 在设备的感光区域内捕获和存储数字形式的图像的成像设备和方法包括在感光区域的每个像素内集成存储单元的阵列。 优选地，存储器单元是双端口存储器单元，使得可以以并行方式执行写入操作，同时以串行方式执行读取操作。 在优选实施例中，每个阵列包含足够数量的存储器单元以存储表示光信号和参考信号的两个数字字。 与计数器一致操作的每个像素内的比较器和斜坡发生器以数字形式捕获光信号和参考信号。 成像装置的设计允许光敏区域中的每个像素以并行方式捕获和存储信号。 该装置的并行功能增加了电子快门速度，而集成存储器阵列消除了对外部帧缓冲存储器的需要。

公开(公告)号：US06545711B1

公开(公告)日：2003-04-08

申请号：US09184426

申请日：1998-11-02

Applicant: Frederick A. Perner ,  Min Cao ,  Charles M. C. Tan ,  Jeremy A. Theil

Inventor： Frederick A. Perner ,  Min Cao ,  Charles M. C. Tan ,  Jeremy A. Theil

IPC: H04N5335

CPC classification number: H01L27/14603

Abstract: An image sensor array. The image sensor array includes a substrate. An array of photo diode sensors are electrically interconnected to the substrate. The photo diode sensors conduct charge at a rate proportional to the intensity of light received by the photo diode sensors. A ring of guard diodes are located around the periphery of the array of photo diode sensors. Each guard diode has a guard diode anode connected to a predetermined guard anode voltage and a guard diode cathode connected to a static guard cathode voltage.

Abstract translation: 图像传感器阵列。 图像传感器阵列包括基板。 一组光电二极管传感器与衬底电互连。 光电二极管传感器以与光电二极管传感器接收的光强成比例的速率传导电荷。 保护二极管环位于光电二极管传感器阵列周围的周围。 每个保护二极管具有连接到预定保护阳极电压的保护二极管阳极和连接到静态保护阴极电压的保护二极管阴极。

公开(公告)号：US06534841B1

公开(公告)日：2003-03-18

申请号：US10017567

申请日：2001-12-14

Applicant: Andrew L. Van Brocklin ,  Kenneth J. Eldredge ,  S. Jonathan Wang ,  Frederick A Perner ,  Peter Fricke

Inventor： Andrew L. Van Brocklin ,  Kenneth J. Eldredge ,  S. Jonathan Wang ,  Frederick A Perner ,  Peter Fricke

IPC: H01L2900

CPC classification number: H01L23/5252 ,  H01L27/10 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.

Abstract translation: 存储器结构具有未图案化并夹在多个反熔丝电极对中的每一个之间的反熔丝材料。 反熔丝材料在反熔丝电极对之间是连续的。 此外，本发明包括一种存储结构，该存储结构包括形成多个行导体的多个反熔丝电极对以及与多个控制元件电连通的多个中间导体。

公开(公告)号：US06317375B1

公开(公告)日：2001-11-13

申请号：US09652807

申请日：2000-08-31

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C700

CPC classification number: G11C7/067 ,  G11C11/16

Abstract: A sense amplifier applies an operating potential to a selected bit line and an equal potential to a subset of unselected lines during a read operation on a memory cell in a resistive cross point array of an information storage device. Before a resistance state of the selected memory cell is sensed, however, an input of the sense amplifier is forced to a known, consistent condition. The sense amplifier input may be forced to the known, consistent condition by pulling up the input to an array voltage.

Abstract translation: 感测放大器在对信息存储设备的电阻交叉点阵列中的存储器单元的读取操作期间将所选择的位线的操作电位施加到未选择线的子集的相等电位。 然而，在检测到所选存储单元的电阻状态之前，将感测放大器的输入强制为已知的一致条件。 通过将输入提升到阵列电压，读出放大器输入可能被迫到已知的一致条件。

公开(公告)号：US06262703B1

公开(公告)日：2001-07-17

申请号：US09195032

申请日：1998-11-18

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G09G336

CPC classification number: G09G3/3648 ,  G09G3/20 ,  G09G3/3614 ,  G09G2300/0823 ,  G09G2300/0842

Abstract: A pixel within an array of pixels in which each pixel cell includes circuitry for generating its own DC balance data by utilizing the display data that is transferred to the pixel from an external source. Each pixel cell includes an initial storage node that branches into two separate storage nodes, the first of the branched nodes being used to store data that is used for display by the pixel and the second of the branched nodes being used to generate and hold the DC balance data. Once the display data has been displayed by the pixel, the DC balance data is multiplexed to the pixel and the pixel is driven according to the DC balance data. Generating the DC balance data within a pixel cell, instead of transferring DC balance data to the pixel cell from an external source, reduces the data transfer load to the pixel cell by approximately one-half.

Abstract translation: 像素阵列内的像素，其中每个像素单元包括通过利用从外部源传送到像素的显示数据来生成其自己的DC平衡数据的电路。 每个像素单元包括分支到两个单独存储节点的初始存储节点，第一分支节点用于存储用于由像素显示的数据，并且第二分支节点用于生成和保持DC 余额数据。 一旦像素显示显示数据，则直流平衡数据被复用到像素，并且根据直流平衡数据来驱动像素。 在像素单元内生成DC平衡数据，而不是将DC平衡数据从外部源传输到像素单元，将数据传输负载减少到像素单元大约一半。

公开(公告)号：US06256224B1

公开(公告)日：2001-07-03

申请号：US09564713

申请日：2000-05-03

Applicant: Frederick A Perner ,  Kenneth J Eldredge ,  Lung T Tran

Inventor： Frederick A Perner ,  Kenneth J Eldredge ,  Lung T Tran

IPC: G11C1115

CPC classification number: G11C11/16 ,  G11C11/15

Abstract: A write circuit for a large array of memory cells of a Magnetic Random Access Memory (“MRAM”) device. The write circuit can provide a controllable, bi-directional write current to selected word and bit lines without exceeding breakdown limits of the memory cells. Additionally, the write circuit can spread out the write currents over time to reduce peak currents.

Abstract translation: 用于磁随机存取存储器（“MRAM”）器件的大量存储器单元的写入电路。 写入电路可以在不超过存储器单元的击穿极限的情况下向所选择的字和位线提供可控的双向写入电流。 此外，写入电路可以随着时间推移写入电流以减少峰值电流。