公开(公告)号：US20140359209A1

公开(公告)日：2014-12-04

申请号：US14374776

申请日：2012-01-30

Applicant: Frederick A. Perner ,  Matthew D. Pickett

Inventor： Frederick A. Perner ,  Matthew D. Pickett

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/407 ,  G11C11/412 ,  G11C19/28

Abstract: Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.

Abstract translation: 字移位静态随机存取存储器（WS-SRAM）单元，字移动静态随机存取存储器（WS-SRAM）和使用该方法的方法采用动态存储模式切换来移位数据。 WS-SRAM单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元，动态/静态（D / S）模式选择器，用于可选择地在动态存储器之间切换WS-SRAM单元 模式和静态存储模式，以及列选择器，可选地确定WS-SRAM单元是否接受移位数据。 WS-SRAM包括排列成阵列的多个WS-SRAM单元和用于移位数据的控制器。 该方法包括切换存储模式并激活列表选择器，将数据从相邻的存储器单元耦合到并将所耦合的数据存储在所选择的WS-SRAM单元中。

公开(公告)号：US07446683B2

公开(公告)日：2008-11-04

申请号：US11267705

申请日：2005-11-03

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: H03M1/00

CPC classification number: G05F3/262

Abstract: A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.

Abstract translation: 提供了用于镜像参考电流的数字电流源。 数字控制的模拟电流源将来自主镜晶体管的电流相乘，产生作为参考电流的数字控制倍数的输出电流。 电路包括多个一位电流镜单元。 每一位电流镜单元包括反射镜晶体管，其接收来自主镜晶体管的模拟栅极电压并提供漏极电压;运算放大器，被配置为保持反射镜晶体管的漏极电压等于模拟栅极电压;以及开关配置 为了接收一个控制位，当镜电压基本上等于主镜电压时，该开关启用电流镜像。 数字电流源还包括用于从一个位电流镜单元中的每一个接收和编译电流的公共线求和元件。

公开(公告)号：US07304887B2

公开(公告)日：2007-12-04

申请号：US10934243

申请日：2004-09-03

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C11/14

CPC classification number: H01L27/228 ,  G11C11/15 ,  G11C11/16

Abstract: A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device. The method of fabricating the memory device includes fabricating a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, fabricating a second layer of MRAM memory cells over the first layer of MRAM memory cells, and fabricating a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device.

Abstract translation: 存储器件包括根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储器单元的第一层上制造的第二层MRAM存储器单元，以及与MRAM存储器的第一层相关联的公共连接 单元和有助于存储器件操作的第二层MRAM存储器单元。 制造存储器件的方法包括制造根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储单元的第一层上制造第二层MRAM存储器单元，以及制造与第一层MRAM存储单元相关联的公共连接 MRAM存储器单元层和有助于存储器件的操作的MRAM存储器单元的第二层。

公开(公告)号：US07130235B2

公开(公告)日：2006-10-31

申请号：US10934719

申请日：2004-09-03

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C7/02

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C8/10 ,  G11C11/16

Abstract: A gain stage in a sense amplifier receives an input signal representing a stored value and senses if the input signal is less than or not less than a reference signal and generates an output signal indicative of a first state when the input signal is less than the reference signal and an output signal indicative of a second state when the input signal is not less than the reference signal. The gain stage further comprises an integrated latch configured to latch the output signal in either the first or second state. Additionally, a controller operates a sense amplifier having multiple operating modes. Sample mode switch logic causes the sense amplifier to sample a first voltage applied to the sense amplifier's input and hold and compare mode switch logic causes the sense amplifier to hold the first voltage for comparison with a second voltage applied to the sense amplifier's input.

Abstract translation: 读出放大器中的增益级接收表示存储值的输入信号，并感测输入信号是否小于或小于参考信号，并且当输入信号小于参考值时产生表示第一状态的输出信号 信号和表示输入信号不小于参考信号时的第二状态的输出信号。 增益级还包括被配置为在第一或第二状态下锁存输出信号的集成锁存器。 另外，控制器操作具有多个操作模式的读出放大器。 采样模式开关逻辑使得读出放大器对施加到读出放大器的输入端的第一电压进行采样并保持并且比较模式开关逻辑使得读出放大器保持第一电压以与施加到读出放大器输入的第二电压进行比较。

公开(公告)号：US07102921B2

公开(公告)日：2006-09-05

申请号：US10843787

申请日：2004-05-11

Applicant: Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee ,  Robert G Walmsley

Inventor： Thomas C. Anthony ,  Frederick A. Perner ,  Heon Lee ,  Robert G Walmsley

IPC: G11C11/14

CPC classification number: G11C11/16 ,  G11C11/1675

Abstract: The present invention provides a magnetic memory device that includes a magnetic memory cell switchable between two states by the application of a magnetic field wherein the magnetic field for such switching is dependent in part on a memory cell temperature. The device further includes at least one heater element proximate to the magnetic memory cell and series connected with the magnetic memory cell for heating of the magnetic memory cell. The device also includes a circuit for selectively applying the electrical current through the at least one heater element so as to heat the cell and facilitate cell state-switching.

Abstract translation: 本发明提供了一种磁存储器件，其包括通过施加磁场在两个状态之间切换的磁存储器单元，其中用于这种切换的磁场部分地取决于存储单元温度。 该装置还包括靠近磁存储器单元的至少一个加热器元件，并且与磁存储单元连接的用于加热磁存储单元的串联。 该装置还包括用于选择性地施加电流通过至少一个加热器元件以便加热电池并促进电池状态切换的电路。

公开(公告)号：US07031185B2

公开(公告)日：2006-04-18

申请号：US11171694

申请日：2005-06-30

Applicant: Frederick A. Perner ,  Andrew L. VanBrocklin ,  Warren B. Jackson

Inventor： Frederick A. Perner ,  Andrew L. VanBrocklin ,  Warren B. Jackson

IPC: G11C11/14

CPC classification number: G11C11/16 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/78 ,  H01L27/224 ,  H01L27/24

Abstract: A resistive cross point memory cell array comprising a plurality of word lines, a plurality of bit lines, a plurality of cross points formed by the word lines and the bit lines, and a plurality of memory cells, each of the memory cells being located at a different one of the cross points, wherein a first bit line comprises a distributed series diode along an entire length of the bit line such that each of the associated memory cells located along the first bit line is coupled between the distributed series diode and an associated word line.

Abstract translation: 一种电阻交叉点存储单元阵列，包括多个字线，多个位线，由字线和位线形成的多个交叉点，以及多个存储单元，每个存储器单元位于 交叉点中的不同的一个，其中第一位线包括沿着位线的整个长度的分布式串联二极管，使得沿着第一位线定位的每个相关联的存储器单元耦合在分布式串联二极管和相关联的 字线。

公开(公告)号：US07027318B2

公开(公告)日：2006-04-11

申请号：US10449572

申请日：2003-05-30

Applicant: Kenneth K. Smith ,  Frederick A. Perner

Inventor： Kenneth K. Smith ,  Frederick A. Perner

IPC: G11C11/00

CPC classification number: G11C5/147

Abstract: A method and apparatus are disclosed for adjusting the offset voltage of a circuit. In one embodiment, the method comprises: supplying reference and supply voltages to the circuit, controlling a voltage across a memory element to be approximately equal to the reference voltage, comparing the current through the memory element to a predetermined value, and adjusting an offset voltage of the circuit, where the offset may remain substantially constant despite changes in the supply voltage.

Abstract translation: 公开了一种用于调整电路的偏移电压的方法和装置。 在一个实施例中，该方法包括：向电路提供参考电压和电源电压，将存储元件两端的电压控制为近似等于参考电压，将通过存储元件的电流与预定值进行比较，并调整偏移电压 的电路，其中尽管电源电压发生变化，但是偏移可能保持基本恒定。

公开(公告)号：US20060044878A1

公开(公告)日：2006-03-02

申请号：US10933039

申请日：2004-09-02

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C7/10

CPC classification number: G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2213/77

Abstract: Programming of a programmable resistive memory device includes supplying programming power to the device; generating feedback as to when the device has been programmed; and removing the programming power when the feedback indicates that the device has been programmed.

Abstract translation: 可编程电阻性存储器件的编程包括向器件提供编程电源; 产生关于设备何时被编程的反馈; 并且当反馈指示设备已被编程时，去除编程电源。

公开(公告)号：US06954373B2

公开(公告)日：2005-10-11

申请号：US10609278

申请日：2003-06-27

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C11/14 ,  G11C11/00

CPC classification number: G11C11/14

Abstract: A system and method for determining the logic state of a magnetic tunnel junction (MTJ) memory device. The method includes applying a first bias voltage to a selected line and measuring a first induced voltage across the MJT device or a memory cell. The method also includes applying a second bias voltage to the selected line, the second bias voltage being different from the first bias voltage, and measuring a second induced voltage across the MJT device. The method also includes comparing a function of the first bias voltage, the first induced voltage, the second bias voltage, and the second induced voltage to a threshold value.

Abstract translation: 一种用于确定磁性隧道结（MTJ）存储器件的逻辑状态的系统和方法。 该方法包括将第一偏置电压施加到所选择的线并测量跨越MJT器件或存储器单元的第一感应电压。 该方法还包括向所选择的线施加第二偏置电压，第二偏置电压不同于第一偏置电压，以及测量跨越MJT器件的第二感应电压。 该方法还包括将第一偏置电压，第一感应电压，第二偏置电压和第二感应电压的功能与阈值进行比较。

公开(公告)号：US06937504B2

公开(公告)日：2005-08-30

申请号：US10725803

申请日：2003-12-02

Applicant: Frederick A. Perner

Inventor： Frederick A. Perner

IPC: G11C11/15 ,  G11C7/04 ,  G11C7/22 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16 ,  G11C29/00 ,  H01L21/8246 ,  H01L27/105

CPC classification number: G11C11/16

Abstract: The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude of write current for writing to the magnetic memory cell, and calculating the selected magnitude of magnetic memory cell write current based on the minimal magnitude of write current and the maximal magnitude of write current.

Abstract translation: 本发明包括用于选择磁存储单元写入电流的期望幅度的装置和方法。 该方法包括确定用于写入磁存储器单元的写入电流的最小幅度，确定用于写入磁存储单元的写入电流的最大幅度，以及基于最小幅度来计算所选择的磁存储单元写入电流的大小 写入电流和写入电流的最大幅度。