公开(公告)号：US06403419B1

公开(公告)日：2002-06-11

申请号：US09717049

申请日：2000-11-22

Applicant: Ki Jun Kim ,  Young Ki Shin ,  Byung Soo Park ,  Hee Youl Lee

Inventor： Ki Jun Kim ,  Young Ki Shin ,  Byung Soo Park ,  Hee Youl Lee

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: There is disclosed a method of manufacturing a flash memory device by which an insulating film spacer is formed on both sidewalls of a gate electrode and a drain region is then formed. Thus, the present invention can improve coverage during a deposition process for forming a select gate and reduce the overlapping area of a floating gate and a drain region. Therefore, as the resistance of the select gate itself is reduced depending on the coverage, the present invention can increase the operating speed of a device and can improve the erase characteristic by F-N tunneling due to reduced overlapping area.

Abstract translation: 公开了一种制造闪存器件的方法，通过该方法，在栅电极的两个侧壁上形成绝缘膜间隔物，然后形成漏极区域。 因此，本发明可以改善用于形成选择栅极的沉积工艺中的覆盖，并且减小浮置栅极和漏极区域的重叠面积。 因此，由于根据覆盖范围减小了选择栅极本身的电阻，本发明可以提高器件的工作速度，并且可以通过减少重叠面积的F-N隧穿来提高擦除特性。

公开(公告)号：US08537632B2

公开(公告)日：2013-09-17

申请号：US13095156

申请日：2011-04-27

Applicant: Hea Jong Yang ,  Hee Youl Lee ,  Sung Jae Chung ,  Hyun Heo ,  Jeong Hyong Yi ,  Yong Dae Park

Inventor： Hea Jong Yang ,  Hee Youl Lee ,  Sung Jae Chung ,  Hyun Heo ,  Jeong Hyong Yi ,  Yong Dae Park

IPC: G11C7/00

CPC classification number: G11C16/0483 ,  G11C16/16 ,  G11C16/32

Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.

Abstract translation: 擦除半导体存储器件的方法包括：基于相邻字线之间的干扰强度将每个存储器块的多个字线分组成至少两组; 通过对所选择的存储块的所有字线施加接地电压并通过向所选存储块的阱施加擦除电压来执行擦除操作; 并且在擦除操作期间首先将一组组的接地电压增加到正电压。

公开(公告)号：US20120061770A1

公开(公告)日：2012-03-15

申请号：US13298096

申请日：2011-11-16

Applicant: Hee Youl Lee ,  Jae Yoon Noh

Inventor： Hee Youl Lee ,  Jae Yoon Noh

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/26586 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

Abstract translation: 一种制造非易失性存储器件的方法，其中在半导体衬底上形成第一栅极线和第二栅极线。 第一栅极线以第一宽度彼此间隔开，第二栅极线以第二宽度彼此间隔开，并且第一宽度比第二宽度宽。 执行在第一栅极线和第二栅极线之间的半导体衬底中形成第一结区域的第一离子注入工艺。 然后执行在第一栅极线之间的各个第一结区域中形成第二结区域的第二离子注入工艺。

公开(公告)号：US20120008361A1

公开(公告)日：2012-01-12

申请号：US13176775

申请日：2011-07-06

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C5/06

CPC classification number: G11C16/0483 ,  G11C16/3418

Abstract: A semiconductor memory device includes cell gate lines arranged in parallel over a semiconductor substrate, gate lines for select transistors disposed over the semiconductor substrate adjacent to the gate lines of the outermost memory cells, from among the gate lines for the memory cells, and metal lines coupled to the select transistors through contacts.

Abstract translation: 半导体存储器件包括在半导体衬底上平行布置的单元栅极线，用于存储单元的栅极线之间的与最外存储单元的栅极线相邻的半导体衬底上的选择晶体管的栅极线和金属线 通过触点耦合到选择晶体管。

公开(公告)号：US08036039B2

公开(公告)日：2011-10-11

申请号：US12763127

申请日：2010-04-19

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: A flash memory device includes a memory cell array on which data is stored, and page buffers that are connected to the memory cells through the bit lines and apply one of the first voltage, second voltage or third voltage between the first and second voltage, to the respective bit line when performing the program.

Abstract translation: 闪速存储器件包括存储有数据的存储单元阵列和通过位线连接到存储器单元并将第一和第二电压之间的第一电压，第二电压或第三电压中的一个施加到第一和第二电压之间的页缓冲器， 执行程序时的相应位线。

公开(公告)号：US07990770B2

公开(公告)日：2011-08-02

申请号：US12635226

申请日：2009-12-10

Applicant: Hee Youl Lee ,  Ki Seog Kim

Inventor： Hee Youl Lee ,  Ki Seog Kim

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: In a method of programming a nonvolatile memory device, when a program is performed, a program voltage is applied to a first word line selected for the program. A first pass voltage is applied to three second word lines neighboring the first word line toward a source select line. First and second voltages are applied to third and fourth word lines neighboring the first word line toward the source select line. A second pass voltage is applied to the remaining word lines other than the first to fourth word lines.

Abstract translation: 在非易失性存储器件的编程方法中，当执行程序时，将程序电压施加到为程序选择的第一字线。 将第一通过电压施加到与第一字线相邻的三个第二字线朝向源选择线。 第一和第二电压被施加到与第一字线相邻的第三和第四字线朝向源选择线。 对第一至第四字线以外的剩余字线施加第二通过电压。

公开(公告)号：US20110026330A1

公开(公告)日：2011-02-03

申请号：US12903968

申请日：2010-10-13

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented.

Abstract translation: 在闪存器件的编程方法中，串联中的存储器单元导通以电连接沟道区，第二串中的所有沟道区均匀地通过将地电压施加到连接到第一栅极的第一位线 包括被编程单元的串和向连接到包括程序禁止单元的第二串的第二位线的程序禁止电压。 如果执行程序操作，则在包括程序禁止的单元的第二串内的通道区域中发生通道升压。 因此，可以增加通道增压电位，并且可以防止程序禁止的电池的阈值电压改变的程序干扰现象。

公开(公告)号：US20100329021A1

公开(公告)日：2010-12-30

申请号：US12826123

申请日：2010-06-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3404 ,  G11C16/0408

Abstract: A method of programming a nonvolatile memory device includes inputting program data to page buffers; performing a program operation and a program verification operation until threshold voltages of memory cells included in a selected page reach a target level according to the program data; when the threshold voltages of the memory cells reach the target level, performing an over-program verification operation to determine over-programmed memory cells in the memory cells; and making a determination of whether error checking and correction (ECC) processing for the over-programmed memory cells is feasible.

Abstract translation: 非易失性存储装置的编程方法包括将程序数据输入到页缓冲器; 执行程序操作和程序验证操作，直到所选页面中包括的存储器单元的阈值电压根据程序数据达到目标电平; 当存储器单元的阈值电压达到目标电平时，执行过程编程验证操作以确定存储器单元中的过程编程存储单元; 并且确定对于过度编程的存储器单元的错误校验和校正（ECC）处理是否可行。

公开(公告)号：US20100302862A1

公开(公告)日：2010-12-02

申请号：US12856190

申请日：2010-08-13

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/349

Abstract: The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage.

Abstract translation: 本发明涉及一种操作非易失性存储器件的方法。 在本发明的一个方面，该方法包括对整个存储单元执行第一程序操作，测量参考存储单元的第一编程速度，将第一程序速度存储在程序速度存储单元中，重复执行程序/ 擦除操作，直到编程/擦除操作的数目对应于特定参考值，当编程/擦除操作的数量对应于特定参考值时，测量参考存储器单元的第二编程速度， 第一编程速度和第二编程速度，根据计算出的程序速度差重置程序启动电压，并且基于复位程序启动电压执行编程/擦除操作。

公开(公告)号：US20090086545A1

公开(公告)日：2009-04-02

申请号：US12233241

申请日：2008-09-18

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/06 ,  G11C7/00

CPC classification number: G11C16/349

Abstract: The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage.

Abstract translation: 本发明涉及一种操作非易失性存储器件的方法。 在本发明的一个方面，该方法包括对整个存储单元执行第一程序操作，测量参考存储单元的第一编程速度，将第一程序速度存储在程序速度存储单元中，重复执行程序/ 擦除操作，直到编程/擦除操作的数目对应于特定参考值，当编程/擦除操作的数量对应于特定参考值时，测量参考存储器单元的第二编程速度， 第一编程速度和第二编程速度，根据计算出的程序速度差重置程序启动电压，并且基于复位程序启动电压执行编程/擦除操作。