公开(公告)号：US20100072560A1

公开(公告)日：2010-03-25

申请号：US12562727

申请日：2009-09-18

申请人： Hee Youl Lee ,  Jae Yoon Noh

发明人： Hee Youl Lee ,  Jae Yoon Noh

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

摘要翻译： 一种制造非易失性存储器件的方法，其中在半导体衬底上形成第一栅极线和第二栅极线。 第一栅极线以第一宽度彼此间隔开，第二栅极线以第二宽度彼此间隔开，并且第一宽度比第二宽度宽。 执行在第一栅极线和第二栅极线之间的半导体衬底中形成第一结区域的第一离子注入工艺。 然后执行在第一栅极线之间的各个第一结区域中形成第二结区域的第二离子注入工艺。

公开(公告)号：US20120061770A1

公开(公告)日：2012-03-15

申请号：US13298096

申请日：2011-11-16

申请人： Hee Youl Lee ,  Jae Yoon Noh

发明人： Hee Youl Lee ,  Jae Yoon Noh

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

摘要翻译： 一种制造非易失性存储器件的方法，其中在半导体衬底上形成第一栅极线和第二栅极线。 第一栅极线以第一宽度彼此间隔开，第二栅极线以第二宽度彼此间隔开，并且第一宽度比第二宽度宽。 执行在第一栅极线和第二栅极线之间的半导体衬底中形成第一结区域的第一离子注入工艺。 然后执行在第一栅极线之间的各个第一结区域中形成第二结区域的第二离子注入工艺。

公开(公告)号：US08278178B2

公开(公告)日：2012-10-02

申请号：US12562727

申请日：2009-09-18

申请人： Hee Youl Lee ,  Jae Yoon Noh

发明人： Hee Youl Lee ,  Jae Yoon Noh

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

摘要翻译： 一种制造非易失性存储器件的方法，其中在半导体衬底上形成第一栅极线和第二栅极线。 第一栅极线以第一宽度彼此间隔开，第二栅极线以第二宽度彼此间隔开，并且第一宽度比第二宽度宽。 执行在第一栅极线和第二栅极线之间的半导体衬底中形成第一结区域的第一离子注入工艺。 然后执行在第一栅极线之间的各个第一结区域中形成第二结区域的第二离子注入工艺。

公开(公告)号：US08619472B2

公开(公告)日：2013-12-31

申请号：US13281312

申请日：2011-10-25

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state.

摘要翻译： 一种用于操作闪速存储器件的方法包括将通过电压施加到漏极通过字线，源极字线和未选字线。 漏极通行字线设置在漏极选择线和字线之间。 漏极字线具有与字线相同的结构。 在源选择线和字线之间提供源通过字线。 源通道字线具有与字线相同的结构。 将编程电压施加到与所选择的存储器单元块相关联的选定字线。 接地电压被施加到漏通字线和源通路字线。 与未选择的存储单元块相关联的字线设置为浮动状态。

公开(公告)号：US20110261623A1

公开(公告)日：2011-10-27

申请号：US13095156

申请日：2011-04-27

申请人： Hea Jong YANG ,  Hee Youl Lee ,  Sung Jae Chung ,  Hyun Heo ,  Jeong Hyong Yi ,  Yong Dae Park

发明人： Hea Jong YANG ,  Hee Youl Lee ,  Sung Jae Chung ,  Hyun Heo ,  Jeong Hyong Yi ,  Yong Dae Park

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/32

摘要： A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.

摘要翻译： 擦除半导体存储器件的方法包括：基于相邻字线之间的干扰强度将每个存储器块的多个字线分组成至少两组; 通过对所选择的存储块的所有字线施加接地电压并通过向所选存储块的阱施加擦除电压来执行擦除操作; 并且在擦除操作期间首先将一组组的接地电压增加到正电压。

公开(公告)号：US08045372B2

公开(公告)日：2011-10-25

申请号：US11760767

申请日：2007-06-10

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C16/06 ,  G11C16/08 ,  G11C16/22

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included between the select lines and the word lines. The operating voltage generator outputs operating voltages to global select lines, global word lines and global pass word lines. The block switching unit connects the global word lines to the word lines and the select lines in response to a block select signal. The voltage supply circuit is connected to the select line and the pass word line, and is configured to supply the select line and the pass word line with a ground voltage in response to a block select inverse signal.

摘要翻译： 闪存器件包括多个存储单元块，工作电压发生器，块切换单元和电压供应电路。 多个存储单元块中的每一个都包括选择线和字线，并且具有包括在选择线和字线之间的字线。 工作电压发生器将工作电压输出到全局选择线，全局字线和全局通过字线。 块切换单元响应于块选择信号将全局字线连接到字线和选择线。 电压供给电路连接到选择线和通过字线，并且被配置为响应于块选择反相信号而将选择线和通过字线提供接地电压。

公开(公告)号：US07643338B2

公开(公告)日：2010-01-05

申请号：US11618697

申请日：2006-12-29

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C11/34 ,  G11C11/04

CPC分类号： G11C16/0483

摘要： A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied.

摘要翻译： 一种用于对闪速存储器件进行编程的方法包括将程序偏置应用于存储单元串内的多个存储单元的存储单元。 每个存储器单元串包括源选择线，多个存储单元和漏极选择线。 相对于已经应用了程序偏置的存储单元，在源选择线方向中的至少一个存储单元施加第一通过偏压。 相对于已经施加了第一通过偏压的存储单元，在漏选择线方向上对存储单元施加第二偏压。

公开(公告)号：US07616486B2

公开(公告)日：2009-11-10

申请号：US11965974

申请日：2007-12-28

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/24

摘要： A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line.

摘要翻译： 闪存器件的单元阵列包括第一和第二存储器块单元和电压发生器。 第一和第二存储块单元中的每一个包括具有多个存储单元的多个存储块。 电压发生器向第一和第二存储器单元输出源电压，电源电压和正偏压。 第一和第二存储器块单元通过位线并联连接。

公开(公告)号：US20090168510A1

公开(公告)日：2009-07-02

申请号：US12147165

申请日：2008-06-26

申请人： Hee Youl Lee ,  Won Sic Woo

发明人： Hee Youl Lee ,  Won Sic Woo

IPC分类号： G11C16/06

CPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/3454

摘要： The present invention relates to an operation of a non-volatile memory device. According to a method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting a memory block. As a result of the first program operation, threshold voltages of the memory cells are firstly measured. A second program operation is performed using a second program voltage, which is increased as much as a difference between a first threshold voltage, that is, a lowest voltage level of the firstly measured threshold voltages and a second threshold voltage, that is, an intermediate voltage level of the firstly measured threshold voltages. The second program operation is repeatedly performed by increasing the second program voltage as much as the difference between the first and second threshold voltages until the lowest threshold voltage becomes higher than a program verify voltage. A pass voltage is then set by reflecting a first voltage level, that is, a difference between a program voltage applied in a last program execution step and the first program voltage.

摘要翻译： 本发明涉及一种非易失性存储器件的操作。 根据本发明的一个方面的操作非易失性存储器件的方法，通过对构成存储器块的存储器单元的字线应用第一编程电压来执行第一编程操作。 作为第一编程操作的结果，首先测量存储单元的阈值电压。 使用第二编程电压执行第二编程操作，该第二编程电压被增加到第一阈值电压（即，首先测量的阈值电压的最低电压电平）与第二阈值电压之间的差，即中间 首先测量的阈值电压的电压电平。 通过将第二编程电压与第一和第二阈值电压之间的差异增加直到最低阈值电压变得高于编程验证电压来重复执行第二编程操作。 然后通过反映第一电压电平，即在最后程序执行步骤中施加的编程电压与第一编程电压之间的差异来设置通过电压。

公开(公告)号：US07315472B2

公开(公告)日：2008-01-01

申请号：US11420367

申请日：2006-05-25

申请人： Hee Youl Lee

发明人： Hee Youl Lee

IPC分类号： G11C16/02 ,  G11C8/12 ,  G11C8/14 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C16/24

摘要： A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

摘要翻译： 非易失性存储器件可以包括分别与位线串联连接的存储器单元的多个存储器块。 多个存储块中的每一个可以包括具有分别连接到位线的第一选择晶体管和连接到公共源极线的第二选择晶体管之间的第一组存储器单元的第一子存储器块 以及具有分别连接到位线的第三选择晶体管之间的第二组存储单元的第二子存储块以及连接到公共源极线的第四选择晶体管。