公开(公告)号：US20100120387A1

公开(公告)日：2010-05-13

申请号：US12690532

申请日：2010-01-20

申请人： Henrik T. Jensen ,  Brima B. Ibrahim

发明人： Henrik T. Jensen ,  Brima B. Ibrahim

IPC分类号： H04B1/16 ,  H03H7/00 ,  H04B1/18

CPC分类号： H04L27/38 ,  H03H17/0664 ,  H03H17/0671

摘要： A channel-select decimation filter capable of operating in multiple bandwidth modes includes a first low pass filter stage, a variable gain stage, a subtraction module a second low pass filter stage and a down-sampling module. The first low pass filter stage includes a first programmable delay module for filtering input signals to produce first low pass filtered signals. The variable gain stage applies a programmable gain to the input signals to produce gained input signals. The subtraction module subtracts the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage includes a second programmable delay module for filtering the first stage signals to produce channel-selected signals. The first programmable delay module, second programmable delay module and programmable gain are programmed to implement one of the multiple bandwidth modes.

摘要翻译： 能够在多个带宽模式下工作的频道选择抽取滤波器包括第一低通滤波器级，可变增益级，减法模块，第二低通滤波级和下采样模块。 第一低通滤波器级包括用于滤波输入信号以产生第一低通滤波信号的第一可编程延迟模块。 可变增益级将可编程增益应用于输入信号以产生增益的输入信号。 减法模块从增益输入信号中减去第一低通滤波信号，以产生第一级信号。 第二低通滤波器级包括用于对第一级信号进行滤波以产生通道选择信号的第二可编程延迟模块。 第一可编程延迟模块，第二可编程延迟模块和可编程增益被编程以实现多种带宽模式之一。

公开(公告)号：US20090268847A1

公开(公告)日：2009-10-29

申请号：US12436033

申请日：2009-05-05

申请人： Henrik T. Jensen ,  Hea Joung Kim

发明人： Henrik T. Jensen ,  Hea Joung Kim

IPC分类号： H04L27/12 ,  H04B1/04

CPC分类号： H03C3/0991 ,  H03L7/0898

摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

摘要翻译： 通过确定锁相环的压控振荡器的增益偏移开始校准锁相环的方法。 然后通过基于增益偏移来调节锁相环的电荷泵的电流来继续处理。

公开(公告)号：US07587000B2

公开(公告)日：2009-09-08

申请号：US11958055

申请日：2007-12-17

申请人： Henrik T. Jensen ,  Hong Shi

发明人： Henrik T. Jensen ,  Hong Shi

IPC分类号： H04L27/00

CPC分类号： H03D3/007 ,  H04L27/38

摘要： A radio receiver includes a single analog to digital converter, a 1st digital mixing module, and a 2nd digital mixing module. The single analog to digital converter is coupled to convert the filtered IF signal into a digital IF signal, which includes information regarding an in-phase component and a quadrature component of a modulated RF signal. The 1st and 2nd mixing modules each receive the digital IF signal and mix the digital IF signal with an in-phase and quadrature digital local oscillation to produce a 1st baseband signal component and a 2nd baseband signal component.

摘要翻译： 无线电接收机包括单个模数转换器，第一数字混合模块和第二数字混合模块。 耦合单个模数转换器以将经滤波的IF信号转换成数字IF信号，该数字IF信号包括关于调制RF信号的同相分量和正交分量的信息。 第一和第二混频模块各自接收数字IF信号，并将数字IF信号与同相和正交数字本地振荡混频，以产生第一基带信号分量和第二基带信号分量。

公开(公告)号：US07471737B2

公开(公告)日：2008-12-30

申请号：US11015162

申请日：2004-12-17

申请人： Henrik T. Jensen ,  Paul Anthony Lettieri

发明人： Henrik T. Jensen ,  Paul Anthony Lettieri

IPC分类号： H03C3/00 ,  H04L25/03

CPC分类号： H04L27/368

摘要： A radio frequency (RF) transmitter includes a digital radio processor and a baseband processor. A complex analog-to-digital converter (ADC) within the radio processor provides an analog interface to the baseband processor to receive an analog complex modulated baseband signal and convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. A demodulator within the radio processor demodulates the digital complex modulated baseband signal to recreate the original transmit digital data as a demodulated digital signal. The demodulated digital signal is processed by a digital processor in the radio processor to mitigate the effects of various imperfections in the radio processor circuitry.

摘要翻译： 射频（RF）发射机包括数字无线电处理器和基带处理器。 无线电处理器内的复数模数转换器（ADC）为基带处理器提供模拟接口，以接收模拟复调制基带信号，并将模拟复调制基带信号转换为数字复调制基带信号。 无线电处理器内的解调器解调数字复调制基带信号，以重构原始发射数字数据作为解调数字信号。 解调的数字信号由无线电处理器中的数字处理器处理以减轻无线电处理器电路中各种缺陷的影响。

公开(公告)号：US07397863B2

公开(公告)日：2008-07-08

申请号：US10954911

申请日：2004-09-30

申请人： Henrik T. Jensen

发明人： Henrik T. Jensen

IPC分类号： H04L25/49 ,  H04L7/00

CPC分类号： H04B1/0475 ,  H04L25/03343

摘要： The present invention implements an architecture that changes the sequence of digital processing so that equalization occurs prior to phase accumulation. A phase differentiator receives an envelope path phase signal to produce a differentiated phase signal to an equalizer. The transfer function of the phase differentiator is implemented so that it cancels, except for a one-cycle delay, the transfer function of the phase accumulator. This cancellation substantially eliminates accumulation of the envelop path phase signal. Additionally, a dither signal added to the quantization nodes in the equalizers shifts the spectral content of the quantization noise such that the phase accumulator sees the quantization noise as zero mean white noise. Implemented as one of a rounding or flooring quantizer, biquad filters in the equalizers round or truncate the equalizer output to a minimal bit width based on a desired output phase error.

摘要翻译： 本发明实现了改变数字处理序列以使相位累积之前发生均衡的架构。 相位微分器接收包络线路相位信号以产生到均衡器的微分相位信号。 实现相位微分器的传递函数，使得相位累加器的传递函数除了一个周期的延迟之外取消。 该消除基本上消除了包络路径相位信号的累积。 另外，加到均衡器中的量化节点的抖动信号将量化噪声的频谱内容移位，使得相位累加器将量化噪声视为零平均白噪声。 实现为舍入或地板量化器之一，均衡器中的二进制滤波器基于期望的输出相位误差将均衡器输出舍入或截断到最小位宽度。

公开(公告)号：US07394881B2

公开(公告)日：2008-07-01

申请号：US10911934

申请日：2004-08-05

申请人： Henrik T. Jensen

发明人： Henrik T. Jensen

IPC分类号： H04B1/10

CPC分类号： H04L27/18 ,  H04L25/03133 ,  H04L25/03343 ,  H04L2025/03394 ,  H04L2025/03401

摘要： A radio receiver includes a low noise amplifier, a down conversion module, an analog to digital converter, and a digital demodulator. The digital demodulator is operably coupled to convert the digital low IF signals into inbound digital symbols and includes a baseband conversion module, a filtering module, a programmable equalizer, a CORDIC module, and a demodulation module. The programmable equalizer is operably coupled to equalize phase and frequency response of filtered digital baseband signals from the filtering module such that the phase and frequency response of the filtered digital baseband signals approximates phase and frequency response of a square root raised cosine filter to produce adjusted digital baseband signals. The CORDIC module is operably coupled to produce phase and magnitude information from the adjusted digital baseband signals. The demodulation module is operably coupled to produce the inbound digital symbols from the phase and magnitude information.

摘要翻译： 无线电接收机包括低噪声放大器，下变频模块，模数转换器和数字解调器。 数字解调器可操作地耦合以将数字低IF信号转换成入站数字符号，并且包括基带转换模块，滤波模块，可编程均衡器，CORDIC模块和解调模块。 可编程均衡器可操作地耦合以均衡来自滤波模块的滤波数字基带信号的相位和频率响应，使得经滤波的数字基带信号的相位和频率响应近似于平方根升余弦滤波器的相位和频率响应，以产生经调整的数字 基带信号。 CORDIC模块可操作地耦合以从调整的数字基带信号产生相位和幅度信息。 解调模块可操作地耦合以从相位和幅度信息产生入站数字符号。

公开(公告)号：US07372917B2

公开(公告)日：2008-05-13

申请号：US10944551

申请日：2004-09-17

申请人： Henrik T. Jensen

发明人： Henrik T. Jensen

IPC分类号： H04L25/49 ,  H04B1/04

CPC分类号： H04L27/361 ,  H03C5/00 ,  H03F1/3252 ,  H04L27/2078 ,  H04L27/368

摘要： An RF transmitter includes a digital processor that includes a time shift signal determination block that produces a time shift signal based upon a bleed over power level in an adjacent channel resulting from downstream phase and magnitude mismatch of a primary signal. In one embodiment, the time shift signal determination block includes logic and circuitry for determining a power ratio for a primary signal between a bleed over power level in an adjacent channel and the primary channel. The time shift signal determination block produces the time shift signal to a time shift block that is operably coupled to receive one of an envelope magnitude component and a phase component from a digital signal generation block, wherein the time shift block generates a time shift in at least one of the envelope signal path and the phase signal path based upon the time shift signal.

摘要翻译： RF发射机包括数字处理器，该数字处理器包括时移信号确定块，该时移信号确定块基于由主信号的下游相位和幅度失配导致的相邻信道中的功率电平渗漏而产生时移信号。 在一个实施例中，时移信号确定块包括逻辑和电路，用于确定相邻信道中的渗出功率电平与主信道之间的主信号的功率比。 时移信号确定块产生时移信号到时移模块，该时移块可操作地耦合以从数字信号产生块接收包络幅度分量和相位分量中的一个，其中该时移块产生在 基于时移信号的包络信号路径和相位信号路径中的至少一个。

公开(公告)号：US07324789B2

公开(公告)日：2008-01-29

申请号：US11039116

申请日：2005-01-20

申请人： Henrik T. Jensen

发明人： Henrik T. Jensen

IPC分类号： H04B1/40

CPC分类号： H03L7/0891 ,  H03L7/093 ,  H03L7/1976

摘要： A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by using a digital processor to generate a digital reference signal at a finely-tuned reference frequency. A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal, and a low pass filter filters the analog reference signal to produce a filtered analog reference signal. The frequency synthesizer further includes a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal.

摘要翻译： 在收发器中使用的频率合成器通过使用数字处理器以精细调谐的参考频率产生数字参考信号，产生具有精细频率分辨率和低带内相位噪声的相对高的参考频率。 数模转换器（DAC）将数字参考信号转换为模拟参考信号，低通滤波器对模拟参考信号进行滤波以产生滤波后的模拟参考信号。 频率合成器还包括用于将经滤波的模拟参考信号从IF信号上变频到RF信号的锁相环。

公开(公告)号：US07116729B2

公开(公告)日：2006-10-03

申请号：US10243861

申请日：2002-09-13

申请人： Brima Ibrahim ,  Henrik T. Jensen

发明人： Brima Ibrahim ,  Henrik T. Jensen

IPC分类号： H04L27/14 ,  H04L27/16 ,  H04L27/22

CPC分类号： H04L25/061 ,  H04L25/063 ,  H04L27/0014 ,  H04L2027/003 ,  H04L2027/0053 ,  H04L2027/0065

摘要： A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

公开(公告)号：US07102547B2

公开(公告)日：2006-09-05

申请号：US11069364

申请日：2005-03-01

申请人： Henrik T. Jensen

发明人： Henrik T. Jensen

IPC分类号： H03M7/00

CPC分类号： H03H17/028 ,  G11B20/10 ,  G11B20/10527 ,  G11B2020/10546 ,  G11B2220/2545 ,  G11B2220/913

摘要： The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

摘要翻译： 本发明提供了在诸如CD到DAT转换的高性能应用中的近乎一致的采样率改变的有效方法。 具体地，输入数字信号首先被插值8倍，并且被低通滤波以形成中间信号。 然后采用钳位三次样条内插器（CCSI）算法将中间信号精确地插入中间信号的相邻采样点之间，按照48 kHz输出采样率的要求。 由于重复的理查森外推法得到的高精度衍生值估计，CCSI是高度准确的。 在详细描述的示例CD到DAT转换器中，采用四阶理查森外推法。 由该示例示出，所提出的方法产生期望的性能，在计算上是有效的并且几乎不需要存储。