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    Method and system for calibrating a frequency synthesizer
    5.
    发明授权
    Method and system for calibrating a frequency synthesizer 有权
    用于校准频率合成器的方法和系统

    公开(公告)号：US08836434B2

    公开(公告)日：2014-09-16

    申请号：US13062583

    申请日：2009-09-08

    Applicant: Abdellatif Bellaouar ,  Ahmed R. Fridi ,  Sher Jiun Fang ,  Hamid Safiri

    Inventor： Abdellatif Bellaouar ,  Ahmed R. Fridi ,  Sher Jiun Fang ,  Hamid Safiri

    IPC: H03L7/00 ,  H03L7/197 ,  H03C3/09 ,  H03L7/093

    CPC classification number: H03L7/093 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0991 ,  H03L7/1976

    Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

    Abstract translation: 具有自动校准系统的数字频率合成器。 数字频率合成器通过启动粗略调谐操作来校准，以快速达到接近期望最终频率的初步频率。 然后根据初步频率执行校准程序，以调整频率合成器中的增益。 该测试涉及将一个或多个测试信号应用于频率合成器并测量在频率合成器中产生的信号。 该测量信号对应于初始频率处电路的增益响应。 当预期增益是已知的时，使用相对于测量信号的增益的任何差异来调整频率合成器的电路中的增益，使得实际增益基本上与预期的增益相匹配。

    METHOD AND SYSTEM FOR CALIBRATING A FREQUENCY SYNTHESIZER
    6.
    发明申请
    METHOD AND SYSTEM FOR CALIBRATING A FREQUENCY SYNTHESIZER 有权
    用于校准频率合成器的方法和系统

    公开(公告)号：US20110163815A1

    公开(公告)日：2011-07-07

    申请号：US13062583

    申请日：2009-09-08

    Applicant: Abdellatif Bellaouar ,  Ahmed R. Fridi ,  Sher Jiun Fang ,  Hamid Safiri

    Inventor： Abdellatif Bellaouar ,  Ahmed R. Fridi ,  Sher Jiun Fang ,  Hamid Safiri

    IPC: H03L7/099 ,  H03L7/18

    CPC classification number: H03L7/093 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0991 ,  H03L7/1976

    Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.

    Abstract translation: 具有自动校准系统的数字频率合成器。 数字频率合成器通过启动粗略调谐操作来校准，以快速达到接近期望最终频率的初步频率。 然后根据初步频率执行校准程序，以调整频率合成器中的增益。 该测试涉及将一个或多个测试信号应用于频率合成器并测量在频率合成器中产生的信号。 该测量信号对应于初始频率处电路的增益响应。 当预期增益是已知的时，使用相对于测量信号的增益的任何差异来调整频率合成器的电路中的增益，使得实际增益基本上与预期的增益相匹配。

    Phase Locked Loop and Method Thereof
    7.
    发明申请
    Phase Locked Loop and Method Thereof 有权
    锁相环及其方法

    公开(公告)号：US20110102090A1

    公开(公告)日：2011-05-05

    申请号：US12893662

    申请日：2010-09-29

    Applicant: SHIH-CHIEH YEN ,  Yao-Chi Wang ,  Hsu-Hung Chang

    Inventor： SHIH-CHIEH YEN ,  Yao-Chi Wang ,  Hsu-Hung Chang

    IPC: H03L7/00 ,  H03L7/06

    CPC classification number: H03L7/183 ,  H03C3/0916 ,  H03C3/0975 ,  H03C3/0983 ,  H03C3/0991 ,  H03L7/0898

    Abstract: A phase locked loop (PLL) includes a clock generating circuit, a first phase detecting circuit, a first loop filter, a first VCO, a first mixer and a control circuit. The clock generating circuit generates a first clock signal. The first phase detecting circuit detects a phase difference between an input data signal and a feedback signal and generates a detection output signal according to the phase difference. The first loop filter, coupled to the first phase detecting circuit, generates a first VCO control signal according to the detection output signal. The first mixer, coupled to the first VCO and the clock generating circuit, mixes the output data signal and the first clock signal to generate the feedback data signal. The control circuit, coupled to the clock generating circuit and the first loop filter, for adjusting the first clock signal according to the first VCO control signal to calculate a gain of the first VCO.

    Abstract translation: 锁相环（PLL）包括时钟产生电路，第一相位检测电路，第一环路滤波器，第一VCO，第一混频器和控制电路。 时钟发生电路产生第一时钟信号。 第一相位检测电路检测输入数据信号和反馈信号之间的相位差，并根据相位差生成检测输出信号。 耦合到第一相位检测电路的第一环路滤波器根据检测输出信号产生第一VCO控制信号。 耦合到第一VCO和时钟发生电路的第一混频器混合输出数据信号和第一时钟信号以产生反馈数据信号。 耦合到时钟发生电路和第一环路滤波器的控制电路，用于根据第一VCO控制信号调整第一时钟信号，以计算第一VCO的增益。

    Phase Locked Oscillator And Radar Unit Having The Same
    8.
    发明申请
    Phase Locked Oscillator And Radar Unit Having The Same 有权
    相位锁相振荡器和雷达单元

    公开(公告)号：US20100213993A1

    公开(公告)日：2010-08-26

    申请号：US12709721

    申请日：2010-02-22

    Applicant: Hironobu HONGO

    Inventor： Hironobu HONGO

    IPC: H03L7/08

    CPC classification number: H03L7/18 ,  G01S7/4008 ,  G01S13/345 ,  H03B23/00 ,  H03C3/0991 ,  H03L7/087 ,  H03L7/093

    Abstract: An error detecting unit of a phase-locked oscillator evaluates difference between a reference phase error signal output from a phase detector and a phase error signal actually output from the phase detector when a reference frequency modulation signal is output from a voltage-controlled oscillator and further detects a frequency error of the frequency modulation signal from the voltage-controlled oscillator based on a rate of change of the difference. A correction unit of the phase-locked oscillator calculates an average value of the frequency error in a predetermined section of the frequency modulation signal and corrects center frequency of the frequency modulation signal by correcting the average value to be zero, and changes the rate of change of control voltage per control step based on comparison between at least two frequency errors in one cycle of the frequency modulation signal. Thus frequency shift of the frequency modulation signal is corrected.

    Abstract translation: 当从压控振荡器输出参考频率调制信号时，锁相振荡器的误差检测单元评估从相位检测器输出的参考相位误差信号和实际从相位检测器输出的相位误差信号之间的差值 基于差的变化率来检测来自压控振荡器的频率调制信号的频率误差。 锁相振荡器的校正单元计算频率调制信号的预定部分中的频率误差的平均值，并且通过将平均值校正为零来校正频率调制信号的中心频率，并且改变变化率 通过比较频率调制信号的一个周期中的至少两个频率误差来控制每个控制步骤的控制电压。 因此，频率调制信号的频移被校正。

    Phase locked loop circuit performing two point modulation and gain calibration method thereof
    9.
    发明授权
    Phase locked loop circuit performing two point modulation and gain calibration method thereof 失效
    执行两点调制和增益校准方法的锁相环电路

    公开(公告)号：US07755439B2

    公开(公告)日：2010-07-13

    申请号：US12265395

    申请日：2008-11-05

    Applicant: Hwa Yeal Yu ,  Dong Jin Keum

    Inventor： Hwa Yeal Yu ,  Dong Jin Keum

    IPC: H03C3/06 ,  H03L7/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/093 ,  H03L7/18

    CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/0891 ,  H03L7/093

    Abstract: A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.

    Abstract translation: 用于两点调制的PLL电路包括第一环路滤波器，第二环路滤波器，多个开关装置和校准模块。 第一个环路滤波器在增益校准操作期间对电荷泵的输出电压进行滤波。 第二个环路滤波器在正常运行期间对电荷泵的输出电压进行滤波。 第一环路滤波器具有比第二环路滤波器更宽的带宽，以通过减少锁定时间来执行快速校准。 第一环路滤波器的操作，第二环路滤波器的操作和第一环路滤波器的断开由开关装置的切换操作决定。 在增益校准操作期间，校准模块基于在第一环路滤波器打开之后累积在第一环路滤波器中的频率误差来调整模拟调制数据的增益。

    Method of continuously calibrating the gain for a multi-path angle modulator
    10.
    发明授权
    Method of continuously calibrating the gain for a multi-path angle modulator 失效
    连续校准多路径角度调制器增益的方法

    公开(公告)号：US07636386B2

    公开(公告)日：2009-12-22

    申请号：US11280665

    申请日：2005-11-15

    Applicant: Earl W. McCune, Jr. ,  Wendell B. Sander

    Inventor： Earl W. McCune, Jr. ,  Wendell B. Sander

    IPC: H04B1/38 ,  H04L5/16 ,  H04L27/10 ,  H04L27/18

    CPC classification number: H03C3/0991 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0975

    Abstract: A multiple path angle modulator includes a closed secondary loop added to a main control loop to automatically adjust a scaling factor related to high frequency gain. The main control loop is configured as a primary path to process the low frequency portion of the angle modulation signal, and the secondary loop is configured as an auxiliary path to process the high frequency portions of the angle modulation signal. The secondary loop senses calibration information and uses it to continuously calibrate the gain within the modulation loop in real time while the system performs its primary operation, thereby eliminating the need for a system shut down or calibration specific timing, such as a lapse time, to balance the modulation paths. Calibration is continuously performed as a background process. The angle modulator is applicable to all modulation type systems.

    Abstract translation: 多路径角度调制器包括添加到主控制回路中的闭合次级回路，以自动调整与高频增益相关的缩放因子。 主控制回路被配置为处理角度调制信号的低频部分的主要路径，并且辅助回路被配置为辅助路径以处理角度调制信号的高频部分。 次级回路感测校准信息，并使用它在系统执行其主要操作时实时地连续地校准调制环路内的增益，从而消除对系统关闭或校准特定定时（例如经过时间）的需要， 平衡调制路径。 作为后台进程连续执行校准。 角度调制器适用于所有调制型系统。

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