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    Phase locked loop modulator calibration techniques
    1.
    发明授权
    Phase locked loop modulator calibration techniques 有权
    锁相环调制器校准技术

    公开(公告)号：US07538623B2

    公开(公告)日：2009-05-26

    申请号：US11281165

    申请日：2005-11-16

    申请人： Henrik T. Jensen ,  Hea Joung Kim

    发明人： Henrik T. Jensen ,  Hea Joung Kim

    IPC分类号： H03L7/08 ,  H03L7/099 ,  H04B7/00

    CPC分类号： H03C3/0991 ,  H03L7/0898

    摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

    摘要翻译： 通过确定锁相环的压控振荡器的增益偏移开始校准锁相环的方法。 然后通过基于增益偏移来调节锁相环的电荷泵的电流来继续处理。

    Phase locked loop modulator calibration techniques
    3.
    发明授权
    Phase locked loop modulator calibration techniques 有权
    锁相环调制器校准技术

    公开(公告)号：US07893773B2

    公开(公告)日：2011-02-22

    申请号：US12436033

    申请日：2009-05-05

    申请人： Henrik T. Jensen ,  Hea Joung Kim

    发明人： Henrik T. Jensen ,  Hea Joung Kim

    IPC分类号： H03L7/08 ,  H03L7/099

    CPC分类号： H03C3/0991 ,  H03L7/0898

    摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

    摘要翻译： 通过确定锁相环的压控振荡器的增益偏移开始校准锁相环的方法。 然后通过基于增益偏移来调节锁相环的电荷泵的电流来继续处理。

    PHASE LOCKED LOOP MODULATOR CALIBRATION TECHNIQUES
    4.
    发明申请
    PHASE LOCKED LOOP MODULATOR CALIBRATION TECHNIQUES 有权
    相位锁定调制器校准技术

    公开(公告)号：US20090268847A1

    公开(公告)日：2009-10-29

    申请号：US12436033

    申请日：2009-05-05

    申请人： Henrik T. Jensen ,  Hea Joung Kim

    发明人： Henrik T. Jensen ,  Hea Joung Kim

    IPC分类号： H04L27/12 ,  H04B1/04

    CPC分类号： H03C3/0991 ,  H03L7/0898

    摘要： A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

    摘要翻译： 通过确定锁相环的压控振荡器的增益偏移开始校准锁相环的方法。 然后通过基于增益偏移来调节锁相环的电荷泵的电流来继续处理。

    Digital compensation for nonlinearities in a polar transmitter
    7.
    发明授权
    Digital compensation for nonlinearities in a polar transmitter 有权
    极地发射机的非线性数字补偿

    公开(公告)号：US07961812B2

    公开(公告)日：2011-06-14

    申请号：US12842963

    申请日：2010-07-23

    申请人： Henrik T. Jensen ,  Hooman Darabi ,  Alireza Zolfaghari

    发明人： Henrik T. Jensen ,  Hooman Darabi ,  Alireza Zolfaghari

    IPC分类号： H04L25/03

    CPC分类号： H04B1/0475 ,  H03C5/00 ,  H03F1/0222 ,  H03F1/3241

    摘要： A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal.

    摘要翻译： 极性发射器包括耦合以接收复调制数字信号的数字处理器和从复调制数字信号产生的反馈信号，其可操作以将复调制数字信号与反馈信号进行比较，以确定指示差分的误差信号 在复调制数字信号与反馈信号之间。 数字处理器还可操作以从误差信号产生校正信号，并将校正信号添加到复调制数字信号以产生经校正的复数调制数字信号。

    Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection
    8.
    发明授权
    Complex digital phase locked loop for use in a demodulator and method of optimal coefficient selection 有权
    用于解调器的复数数字锁相环和最佳系数选择方法

    公开(公告)号：US07826564B2

    公开(公告)日：2010-11-02

    申请号：US12234343

    申请日：2008-09-19

    申请人： Henrik T. Jensen

    发明人： Henrik T. Jensen

    IPC分类号： H03D3/18 ,  H03D3/24

    CPC分类号： H03D3/24 ,  H03D2200/0082

    摘要： A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

    摘要翻译： 用于数字解调器的复数数字锁相环包括相位检测器，用于产生指示复数数字输入信号和复数数字反馈信号之间的相位差的相位误差。 将相位误差输入到控制器，该控制器将相位误差乘以所选择的增益因子，以稳定和优化锁相环，并产生用于提取复数字输入信号中存在的频率偏差的输出信号。 输出信号也输入到数控振荡器，该振荡器基于输出信号跟踪复数数字输入信号的相位，并产生复数数字反馈信号。

    Digital modulator for a GSM/GPRS/EDGE wireless polar RF transmitter
    9.
    发明授权
    Digital modulator for a GSM/GPRS/EDGE wireless polar RF transmitter 失效
    用于GSM / GPRS / EDGE无线极性射频发射机的数字调制器

    公开(公告)号：US07515652B2

    公开(公告)日：2009-04-07

    申请号：US10944552

    申请日：2004-09-17

    申请人： Henrik T. Jensen

    发明人： Henrik T. Jensen

    IPC分类号： H04L25/00

    CPC分类号： H04L27/2003 ,  H04L27/2017

    摘要： A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements.

    摘要翻译： 无线电发射机中的数字调制器包括用于在保持频谱掩模要求的同时在高斯最小移频键控（GMSK）和相移键控（PSK）之间切换的电路。 本发明的数字调制器包括分别产生PSK同相和正交符号和GMSK符号的GMSK和PSK符号映射器到脉冲整形块。 基于调制控制信号的相反相位，符号映射器产生调制数据或逻辑零的蒸汽到脉冲整形块。 脉冲整形块对接收到的数据进行滤波并复用数据，使得每个调制数据流在保护时间期间接收非零数据，以避免将会违反频谱掩模要求的调制信号的突然变化。

    Interpolation filter design and application
    10.
    发明授权
    Interpolation filter design and application 失效
    插值滤波器的设计与应用

    公开(公告)号：US07403962B2

    公开(公告)日：2008-07-22

    申请号：US10856024

    申请日：2004-05-28

    申请人： Henrik T. Jensen

    发明人： Henrik T. Jensen

    IPC分类号： G06F17/17

    CPC分类号： H03H17/0671 ,  H03H17/0225

    摘要： A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the interpolation filtering stages based on a first digital signal processing identity to produce a first equivalent interpolation filtering stage. The method continues by manipulating a second one of the interpolation filtering stages based on the first digital signal processing identity to produce a second equivalent interpolation filtering stage. The method continues by simplifying the first and second equivalent interpolation filtering stages to produce at least a simplified portion of the interpolation filter.

    摘要翻译： 用于设计内插滤波器的方法通过将内插滤波分割成级联在一起的多个内插滤波级开始。 多个插值滤波级中的每一个包括上采样级和滤波级。 该方法通过基于第一数字信号处理标识来操纵内插滤波级中的第一个，以产生第一等效插值滤波级来继续。 该方法通过基于第一数字信号处理标识来操纵内插滤波级中的第二个，以产生第二等效内插滤波级来继续。 该方法通过简化第一和第二等效插值滤波级来产生至少简化的内插滤波器部分而继续。