公开(公告)号：US20120151307A1

公开(公告)日：2012-06-14

申请号：US13302688

申请日：2011-11-22

Applicant: Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

Inventor： Francois Abel ,  Claude Basso ,  Jean L. Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

IPC: G06F11/00

CPC classification number: H04L1/0079 ,  H04L1/0061 ,  H04L1/0072

Abstract: Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.

Abstract translation: 公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。 网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。 该系统利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。 系统通过将数据包校验和与第二个校验和进行比较来验证数据包。

公开(公告)号：US07995472B2

公开(公告)日：2011-08-09

申请号：US12348938

申请日：2009-01-06

Applicant: Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

Inventor： Jean L. Calvignac ,  Chih-jen Chang ,  Joseph F. Logan ,  Fabrice J. Verplanken ,  Daniel Wind

IPC: G01R31/08 ,  H04L12/28 ,  H04L12/54

CPC classification number: H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

Abstract translation: 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

公开(公告)号：US20110158254A1

公开(公告)日：2011-06-30

申请号：US12650174

申请日：2009-12-30

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Colin Beaton Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Colin Beaton Verrilli

IPC: H04J3/22

CPC classification number: H04L47/522 ,  H04L47/6215

Abstract: A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, a source is selected in a manner that maintains fairness in the selection process. A corresponding sink is selected for the selected source based on processing efficiency. If, due to assignment constraints, no sink is available for the selected source, the selected source is retained for selection in the next scheduling period, to maintain fairness. In this case, to optimize efficiency, a most efficient currently available sink is identified and a source for providing work to that sink is selected.

Abstract translation: 一种用于从多个源（例如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器的方法和装置。 在给定的处理期间，以选择过程中保持公平的方式选择源。 基于处理效率为所选择的源选择相应的接收器。 如果由于分配限制，所选择的源没有可用的接收器，所选择的源被保留用于在下一个调度周期中进行选择，以保持公平性。 在这种情况下，为了优化效率，识别出最有效的当前可用的接收器，并且选择用于向该接收器提供工作的源。

公开(公告)号：US20110158250A1

公开(公告)日：2011-06-30

申请号：US12650120

申请日：2009-12-30

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Hubertus Franke ,  Terry L. Nelms, II ,  Fabrice Jean Verplanken

IPC: H04L12/56

CPC classification number: H04L49/9047

Abstract: A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.

Abstract translation: 一种用于从多个源（例如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器的方法和装置。 在给定的处理期间，确定可用于接收工作的接收器，并且考虑到任何分配约束来确定用于将工作发送到可用接收器的资源。 从具有可用工作的合格来源和源的重叠中选择单个来源。 可以使用用于并行同时处理所支持的源的子集的分级源调度器来进行该选择。 从可选择的来源可以分配工作的接收端从有资格从所选源接收工作的可用接收器中选择。

公开(公告)号：US07900016B2

公开(公告)日：2011-03-01

申请号：US12024744

申请日：2008-02-01

Applicant: Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Piyush Chaudhary ,  Edward J. Seminaro

Inventor： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Piyush Chaudhary ,  Edward J. Seminaro

IPC: G06F12/10

CPC classification number: G06F13/387 ,  H04L61/2007 ,  H04L61/35

Abstract: An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.

Abstract translation: 提供了一种寻址模式，其中所有资源（包括存储器和设备）都使用互联网协议（IP）地址进行寻址。 任务（例如应用程序）可以分配一个IP地址范围而不是有效的地址范围。 因此，例如，诸如I / O适配器或甚至打印机的处理元件也可以使用IP地址来寻址，而不需要库调用，设备驱动器，固定存储器等。 该寻址模型还可以跨IP互连提供资源的完全虚拟化，从而允许进程通过网络访问I / O设备。

公开(公告)号：US20100153966A1

公开(公告)日：2010-06-17

申请号：US12336329

申请日：2008-12-16

Applicant: Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

Inventor： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

IPC: G06F9/46

CPC classification number: G06F9/4856 ,  G06F9/5066 ,  G06F9/5088

Abstract: A technique for operating a high performance computing cluster includes monitoring workloads of multiple processors. The high performance computing cluster includes multiple nodes that each include two or more of the multiple processors. Workload information for the multiple processors is periodically updated in respective local job tables maintained in each of the multiple nodes. Based on the workload information in the respective local job tables, one or more threads are periodically moved to a different one of the multiple processors.

Abstract translation: 用于操作高性能计算集群的技术包括监视多个处理器的工作负载。 高性能计算集群包括多个节点，每个节点包括多个处理器中的两个或多个。 多个处理器的工作量信息在维护在多个节点中的每个节点的相应本地作业表中周期性地更新。 基于各个本地作业表中的工作负载信息，将一个或多个线程周期性地移动到多个处理器中的不同的一个。

公开(公告)号：US20100153542A1

公开(公告)日：2010-06-17

申请号：US12336312

申请日：2008-12-16

Applicant: Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

Inventor： Lakshminarayana Baba Arimilli ,  Ravi Kumar Arimilli ,  Claude Basso ,  Jean L. Calvignac

IPC: G06F15/173

CPC classification number: G06F9/5088

Abstract: A technique for operating a high performance computing cluster (HPC) having multiple nodes (each of which include multiple processors) includes periodically broadcasting information, related to processor utilization and network utilization at each of the multiple nodes, from each of the multiple nodes to remaining ones of the multiple nodes. Respective local job tables maintained in each of the multiple nodes are updated based on the broadcast information. One or more threads are then moved from one or more of the multiple processors to a different one of the multiple processors (based on the broadcast information in the respective local job tables).

Abstract translation: 用于操作具有多个节点（每个包括多个处理器）的高性能计算群集（HPC）的技术包括：从多个节点中的每个节点到多个节点周期性地广播与多个节点中的每个节点处的处理器利用和网络利用相关的信息 多个节点中的一个。 基于广播信息来更新维护在多个节点中的每个节点的相应的本地作业表。 然后，一个或多个线程从多个处理器中的一个或多个移动到多个处理器中的不同处理器（基于相应的本地作业表中的广播信息）。

公开(公告)号：US07715428B2

公开(公告)日：2010-05-11

申请号：US11669419

申请日：2007-01-31

Applicant: Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

Inventor： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC: H04L12/66 ,  H04J3/16 ,  H04J3/22

CPC classification number: H04L47/50

Abstract: Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

Abstract translation: 提供了用于处理数据处理设备之间的通信的机制。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

公开(公告)号：US20090198837A1

公开(公告)日：2009-08-06

申请号：US12024695

申请日：2008-02-01

Applicant: Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Edward J. Seminaro

Inventor： Ravi K. Arimilli ,  Claude Basso ,  Jean L. Calvignac ,  Edward J. Seminaro

IPC: G06F3/00

CPC classification number: G06F9/45558 ,  G06F2009/45579

Abstract: A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model abstracts an I/O device such that communication intended for the I/O device may be packetized and sent over a network. Thus, a virtualization platform may packetize communication intended for a remotely located I/O device and transmit the packetized communication over a distance, rather than having to make a call to a library, call a device driver, pin memory, and so forth.

Abstract translation: 提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。 为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于 例。 异构处理元件模型抽象出I / O设备，使得针对I / O设备的通信可以被分组并通过网络发送。 因此，虚拟化平台可以打包用于远程位置的I / O设备的通信，并且在一定距离上发送分组化的通信，而不是必须对库进行呼叫，调用设备驱动器，引脚存储器等。

公开(公告)号：US20090080461A1

公开(公告)日：2009-03-26

申请号：US12327761

申请日：2008-12-03

Applicant: PETER I. A. BARRI ,  CLAUDE BASSO ,  JEAN L. CALVIGNAC ,  BRAHMANAND K. GORTI ,  JOSEPH F. LOGAN ,  NATARAJAN VALDHYANATHAN ,  JOHAN G. A. VERKINDEREN

Inventor： PETER I. A. BARRI ,  CLAUDE BASSO ,  JEAN L. CALVIGNAC ,  BRAHMANAND K. GORTI ,  JOSEPH F. LOGAN ,  NATARAJAN VALDHYANATHAN ,  JOHAN G. A. VERKINDEREN

IPC: H04J3/16

CPC classification number: H04L49/25 ,  H04L49/3009 ,  H04L49/40

Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.

Abstract translation: 通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。 帧头中的信息包含用于修改帧中的信息的帧改变命令。 修改包括添加新信息，删除信息和叠加信息。 变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。 存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。