公开(公告)号：US08515376B2

公开(公告)日：2013-08-20

申请号：US13617229

申请日：2012-09-14

Applicant: Kameran Azadet ,  Samer Hijazi ,  Sunitha Kopparthi ,  Albert Molina ,  Ramon Sanchez

Inventor： Kameran Azadet ,  Samer Hijazi ,  Sunitha Kopparthi ,  Albert Molina ,  Ramon Sanchez

IPC: H04B1/06

CPC classification number: H04L25/0202 ,  H04L1/0631 ,  H04L1/20 ,  H04L5/0023 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/021 ,  H04L25/022 ,  H04L25/023 ,  H04L25/025

Abstract: In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions.

Abstract translation: 在一个实施例中，提供接收机用于多输入系统，该多输入系统包括接收天线，其接收与从多个发射天线发射的多个信号相对应的时域信号。 接收机包括：（a）适于将时域信号变换为频域信号的变换单元; （b）信道估计单元，适于基于频域信号和频域导频信号估计与多个发射天线和接收天线之间的各个信道的多个传递函数相对应的组合传递函数 ; 以及（c）信道分离单元，其包括将所述组合传递函数分离成多个估计信道传递函数的多个频域卷积单元。

公开(公告)号：US07913154B2

公开(公告)日：2011-03-22

申请号：US12039474

申请日：2008-02-28

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H03M13/03

CPC classification number: H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract translation: 公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行）的增加的吞吐量相对于先行深度仅具有线性增加的硬件复杂度。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

公开(公告)号：US20090129519A1

公开(公告)日：2009-05-21

申请号：US12359778

申请日：2009-01-26

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H04L27/06

CPC classification number: H04L25/4923 ,  H04L25/03229 ,  H04L2025/03363

Abstract: A method and apparatus are disclosed for joint equalization and decoding of multilevel codes, such as the MLT-3 code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.

Abstract translation: 公开了一种用于联合均衡和解码多级代码的方法和装置，例如在色散信道上传输的MLT-3码。 MLT-3代码被视为由有限状态机使用在各种状态之间具有状态依赖性的网格生成的代码。 超级网格将MLT-3网格与网络格式的通道连接起来。 接收信号的联合均衡和解码可以使用超级格子进行。 公开了一种序列检测器，其使用超级格或相应的缩减状态网格来对接收到的信号进行联合均衡和解码，以解码MLT-3编码的数据位。 可以使用应用最优维特比算法或缩减复杂度序列估计方法（例如缩减状态序列估计（RSSE）算法）的最大似然序列估计来体现序列检测器。

公开(公告)号：US07499498B2

公开(公告)日：2009-03-03

申请号：US11256182

申请日：2005-10-21

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H04L5/12 ,  H04L23/02

CPC classification number: H04L25/03197 ,  H04L25/03235 ,  H04L25/03299

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.

Abstract translation: 公开了一种用于改进缩减复杂度序列估计技术（例如缩减状态序列估计（RSSE））的处理时间的方法和装置。 预先计算RSSE中分支度量值的可能值，以允许流水线化和缩短关键路径。 通过分别预先计算多维网格码的每个维度，预先计算的计算负荷被减少用于多维网格码。 使用预滤波技术通过缩短信道存储器来降低计算复杂度。 公开了一种用于具有长度为L的信道存储器的信道的RSSE的混合存活器存储器架构，其中对应于L个过去的解码周期的幸存者被存储在寄存器交换架构中，并且与随后的解码周期相对应的幸存者被存储在跟踪 （TBA）或注册交换架构（REA）。 符号被映射到信息位以在从第一寄存器交换架构移动到追溯架构（TBA）或第二寄存器交换架构之前减小字大小。

公开(公告)号：US07363576B2

公开(公告)日：2008-04-22

申请号：US11234446

申请日：2005-09-26

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H03M13/03

CPC classification number: H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract translation: 公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行预测）具有增加的吞吐量，相对于先行深度，硬件复杂度只有线性增加。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

公开(公告)号：US07328227B2

公开(公告)日：2008-02-05

申请号：US11359201

申请日：2006-02-22

Applicant: Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

Inventor： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC: G06F7/00

CPC classification number: G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

Abstract: An low power vector summation apparatus is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

Abstract translation: 提供了一种低功率矢量求和装置，用于使用2的补码运算而没有现有技术的高切换活动。 特别地，本发明操作以利用2的补码的符号扩展属性。 提供2的补码减少的表示，以避免符号扩展和符号扩展位的切换。 检测2的补码的最大幅度，并动态生成其缩小表示以表示信号。 通过缩小表示引入的恒定误差也被动态补偿。

公开(公告)号：US20060143259A1

公开(公告)日：2006-06-29

申请号：US11359201

申请日：2006-02-22

Applicant: Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

Inventor： Kameran Azadet ,  Meng-Lin Yu ,  Zhan Yu

IPC: G06F7/38

CPC classification number: G06F7/5443 ,  G06F7/49994 ,  H03H17/0233 ,  H03H17/06

Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

公开(公告)号：US20060039492A1

公开(公告)日：2006-02-23

申请号：US11256182

申请日：2005-10-21

Applicant: Kameran Azadet ,  Erich Haratsch

Inventor： Kameran Azadet ,  Erich Haratsch

IPC: H04L23/02

CPC classification number: H04L25/03197 ,  H04L25/03235 ,  H04L25/03299

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is disclosed for RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture, and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture to the trace-back architecture (TBA) or the second register exchange architecture.

公开(公告)号：US20060017468A1

公开(公告)日：2006-01-26

申请号：US11141337

申请日：2005-05-31

Applicant: Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

Inventor： Kameran Azadet ,  Fuji Yang ,  Chunbing Guo

IPC: H03K19/094

CPC classification number: H04L25/0282 ,  H03K19/09432 ,  H04L25/0274

Abstract: A common-mode shifting circuit for shifting the common-mode output voltage of a CML device to an arbitrary voltage is disclosed. A constant current source is provided at each output of the CML device. The constant current may be a positive or negative current, tending to raise or lower the common-mode output voltage, respectively. The constant current sources are preferably connected to an alternate voltage supply having a higher voltage than that the supply for the CML device. The invention further provides a method for adjusting the output signal of a current-mode logic circuit having two or more output ports, comprising the step of providing a constant current at each output port of the current-mode logic circuit, whereby the common-mode voltage at the output ports of said current-mode logic circuit is level-shifted.

Abstract translation: 公开了一种用于将CML器件的共模输出电压转换为任意电压的共模移位电路。 在CML设备的每个输出端提供恒流源。 恒定电流可以是正或负电流，分别提高或降低共模输出电压。 恒流源优选地连接到具有比CML器件的电源高的电压的交流电压源。 本发明还提供一种用于调整具有两个或多个输出端口的电流模式逻辑电路的输出信号的方法，包括在电流模式逻辑电路的每个输出端口处提供恒定电流的步骤，由此共模 所述电流模式逻辑电路的输出端口处的电压被电平移位。

公开(公告)号：US20050018777A1

公开(公告)日：2005-01-27

申请号：US10610335

申请日：2003-06-30

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: H04L25/02 ,  H04B3/30 ,  H04B3/32 ,  H04L25/03 ,  H04B3/00

CPC classification number: H04B3/32 ,  H04B3/30

Abstract: A method and apparatus are disclosed for reducing noise, such as external noise, cross-talk and echo, in an unbalanced channel. A cross-talk canceller is disclosed that uses a multi-dimensional finite impulse response filter to process both the differential, d, and common-mode, c, components of a received signal. Recovery of the differential mode component of the received signal is improved by reducing the contribution of the common mode component. The common mode component of a received signal may be expressed, for example, as the average of two voltages or two current signals. The differential and common mode components of the received signal are equalized. The disclosed multi-dimensional cross-talk canceller reduces external noise; near-end crosstalk resulting from differential and common mode components on one twisted pair interfering with another twisted pair; and echo crosstalk resulting from differential and common mode cross-talk components on the same twisted pair.

Abstract translation: 公开了一种用于在不平衡通道中降低诸如外部噪声，串扰和回波之类的噪声的方法和装置。 公开了一种使用多维有限脉冲响应滤波器来处理接收信号的差分，差分和共模c分量的串扰消除器。 通过减小共模分量的贡献来提高接收信号的差模分量的恢复。 接收信号的共模分量可以例如表示为两个电压或两个电流信号的平均值。 接收信号的差分和共模分量相等。 所公开的多维串扰消除器减少外部噪声; 一对双绞线上的差模和共模分量产生的近端串扰干扰另一双绞线; 以及由相同双绞线上的差分和共模串扰组件产生的回声串扰。