公开(公告)号：US20080024192A1

公开(公告)日：2008-01-31

申请号：US11460349

申请日：2006-07-27

Applicant: Kiyoshi Kase ,  Dzung T. Tran

Inventor： Kiyoshi Kase ,  Dzung T. Tran

IPC: H03K17/00

CPC classification number: H03K17/693 ,  H03K17/005 ,  H03K17/6871 ,  H03K2217/0036

Abstract: A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Abstract translation: 电压控制电路包括耦合到具有第一电压的第一电压源端子的第一晶体管，耦合到第一晶体管的第二晶体管和节点，耦合到第二电压源端子和节点的第三晶体管，其中第二电压 供电端子具有第二电压，并且节点处于从由第一电压和第二电压组成的组中选择的电压，以及耦合到节点的第四晶体管。

公开(公告)号：US07116147B2

公开(公告)日：2006-10-03

申请号：US10967898

申请日：2004-10-18

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K5/1504 ,  H03K2005/00039

Abstract: A circuit and a method for interpolative delay is provided. The circuit includes a delay locked loop with interpolation delay. The delay locked loop includes a differential inverter, an interpolation circuit, and a differential compare circuit. The differential inverter is coupled to receive a differential clock signal and coupled to provide an inverted differential clock signal. The interpolation circuit is coupled to receive both the clock signal and the inverted clock signal, and to provide an interpolated clock signal having a first delay relative to the clock signal. The differential compare circuit is coupled to receive the inverted clock signal and coupled to provide a non-interpolated clock signal having a second delay relative to the clock signal. The second delay corresponds to a full delay of the differential inverter and the first delay corresponds to a predetermined fraction of the full delay.

Abstract translation: 提供了一种用于内插延迟的电路和方法。 该电路包括具有插值延迟的延迟锁定环。 延迟锁定环路包括差分逆变器，内插电路和差分比较电路。 差分反相器耦合以接收差分时钟信号并被耦合以提供反相差分时钟信号。 内插电路被耦合以接收时钟信号和反相时钟信号，并提供相对于时钟信号具有第一延迟的内插时钟信号。 差分比较电路被耦合以接收反相时钟信号并被耦合以提供相对于时钟信号具有第二延迟的非内插时钟信号。 第二延迟对应于差分逆变器的完全延迟，并且第一延迟对应于完全延迟的预定分数。

公开(公告)号：US06906582B2

公开(公告)日：2005-06-14

申请号：US10652530

申请日：2003-08-29

Applicant: Kiyoshi Kase ,  May Len

Inventor： Kiyoshi Kase ,  May Len

IPC: G05F1/56 ,  G05F1/10

CPC classification number: G05F1/56

Abstract: In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuation at each block. The power voltage(s) of the overall circuit may be globally regulating in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.

Abstract translation: 在包括多个功能块电路的电路中，每个块具有最小工作电压，来自每个块的多条感测线用于测量每个块处的局部电压波动。 整个电路的电源电压可以响应于这种局部检测的电压波动在电路中进行全局调节，以防止局部电压降低到每个块的最小工作电压以下。

公开(公告)号：US20050046467A1

公开(公告)日：2005-03-03

申请号：US10652530

申请日：2003-08-29

Applicant: Kiyoshi Kase ,  May Len

Inventor： Kiyoshi Kase ,  May Len

IPC: G05F1/56 ,  G05F1/10

CPC classification number: G05F1/56

Abstract: In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuations at each block. The power voltage(s) of the overall circuit may be globally regulated in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.

Abstract translation: 在包括多个电路功能块的电路中，每个块具有最小工作电压，来自每个块的多条感测线用于测量每个块处的局部电压波动。 响应于这种局部感测的电压波动，整个电路的电源电压可以在电路中被全局调节，以防止局部电压降低到每个块的最小工作电压以下。

公开(公告)号：US06198314B1

公开(公告)日：2001-03-06

申请号：US09236064

申请日：1999-01-25

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: G11C2702

CPC classification number: G11C27/024

Abstract: A sample and hold circuit (200) accepts an input (202). During a first half of the clock (204) (either an active high portion or an active low portion) the devices (216, 220, and 222) drive the node (218) to a voltage representative of the voltage present on input (202). At a rising edge of the clock (204), the switch (222) is disabled and the voltage on the node (218) is forced to a higher hold voltage by a capacitor (224). While sample circuit (208) is holding the high voltage on node (218), a hold circuit (210) is settling to a hold voltage representative of the voltage on node (218) in a master-slave fashion. This manner of clocking and controlling the circuit (200) allows circuit (200) to be used in low power, high speed telecommunications systems.

Abstract translation: 采样和保持电路（200）接受输入（202）。 在第一半时钟（204）（有效高部分或有效低电平部分）期间，器件（216,220和222）将节点（218）驱动到表示输入（202）上存在的电压的电压 ）。 在时钟（204）的上升沿，开关（222）被禁止，并且节点（218）上的电压被电容器（224）强制到更高的保持电压。 当采样电路（208）保持节点（218）上的高电压时，保持电路（210）以主从方式建立到表示节点（218）上的电压的保持电压。 时钟和控制电路（200）的这种方式允许电路（200）用于低功率，高速电信系统中。

公开(公告)号：US5559500A

公开(公告)日：1996-09-24

申请号：US401751

申请日：1995-03-09

Applicant: Kiyoshi Kase

Inventor： Kiyoshi Kase

IPC: G01R19/165 ,  G01R31/40 ,  H02H3/087 ,  G08B21/00

CPC classification number: H02H3/087 ,  G01R19/16538 ,  G01R31/40

Abstract: An overcurrent is detected with small power consumption and at a high level of accuracy. A first transistor section 3 comprised of one NPN transistor 31 and a second transistor section 4 comprised of four NPN transistors 41-44 having the same characteristics as those of the transistor 31 are connected across a current sense resistor 2, with their emitters connected to the resistor 2. The transistors 31 and 41-44 have their bases commonly connected, with a voltage applied between their base and emitter by a voltage application unit 5, and have their collectors connected to transistors 61 and 62 which form a current mirror circuit. Once a bandgap voltage, .DELTA.V.sub.BE, i.e., a voltage difference between the base-emitter voltages of the transistor sections 3 and 4, is determined, the current density ratio of both the transistor sections 3 and 4 is determined, which is used to detect an overcurrent.

Abstract translation: 以低功耗和高精度检测过电流。 由具有与晶体管31相同特性的四个NPN晶体管41-44构成的一个NPN晶体管31和第二晶体管部分4构成的第一晶体管部分3连接在电流检测电阻器2上，其发射极连接到 晶体管31和41-44的基极共同连接，电压施加单元5在其基极和发射极之间施加电压，并且其集电极连接到形成电流镜电路的晶体管61和62。 一旦确定了带隙电压DELTA VBE，即晶体管部分3和4的基极 - 发射极间电压之间的电压差，则确定两个晶体管部分3和4的电流密度比，这被用于检测 过电流

公开(公告)号：US5057999A

公开(公告)日：1991-10-15

申请号：US370980

申请日：1989-06-26

Applicant: Kiyoshi Kase ,  Minoru Suzuki

Inventor： Kiyoshi Kase ,  Minoru Suzuki

IPC: G06F9/38 ,  G06F11/00

CPC classification number: G06F9/3802 ,  G06F11/004 ,  G06F11/0757 ,  G06F11/0763

Abstract: A microprocessor including a CPU, an instruction memory (ROM) with a sequencer in the CPU that sends out a fetch signal for an instruction, and an address decoder that decodes the fetch signal and sends a signal to the ROM allowing the fetch signal to fetch an instruction if the address is correct.