公开(公告)号：US06591325B1

公开(公告)日：2003-07-08

申请号：US09547392

申请日：2000-04-11

申请人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1314

CPC分类号： G06F13/4204

摘要： An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.

摘要翻译： 一种在多个系统模块之间传送交易的信息处理系统。 请求侧模块中的请求侧接口单元具有请求ID队列，其中发出的请求事务按照发布的顺序存储。 请求侧队列指针指向与要接受的响应事务相对应的该请求ID队列中的条目。 响应侧模块中的响应侧接口单元具有响应队列，其中接受请求事务按接受顺序存储。 响应侧队列指针指向对应于接下来要发出的响应事务的该响应队列中的条目。 因此，在请求侧接口单元和响应侧接口单元之间传送请求事务和相应的响应事务，而不转移事务ID。 当响应顺序改变时，响应侧接口单元发出改变请求侧队列指针的值的命令，以通知请求侧接口单元的顺序改变。

公开(公告)号：US6065111A

公开(公告)日：2000-05-16

申请号：US120911

申请日：1993-09-15

申请人： Tatsuo Higuchi ,  Naoki Hamanaka

发明人： Tatsuo Higuchi ,  Naoki Hamanaka

IPC分类号： G06F12/08 ,  G06F7/38

CPC分类号： G06F12/0813

摘要： A processor for a multiprocessor system, such as a parallel processor system, connected to a network has a sending unit and a receiving unit for transferring and receiving data to and from the network as well as a receive cache and a main cache. When data is received from the network, it is determined whether a hit or miss occurs to the main cache and receive cache, respectively. If a hit to the receive cache occurs, then the receive cache controller stores the data directly in the receive cache as it is received. When a hit to the main cache occurs, an intercache transfer is executed for transferring the hit block in the main cache to the receive cache so that the data can be stored in the receive cache. When an instruction processor requests access to data held in the receive cache, the data is retrieved to the instruction processor and at the same time transferred to a main cache.

摘要翻译： 连接到网络的诸如并行处理器系统的多处理器系统的处理器具有发送单元和用于向网络以及从网络传送数据和从网络接收数据的接收单元以及接收缓存和主缓存。 当从网络接收到数据时，确定是否发生命中或未命中到主缓存和接收缓存。 如果发生对接收缓存的命中，则接收高速缓存控制器在接收到高速缓存时将数据直接存储在接收缓存中。 当发生对主缓存的命中时，执行间隙传送以将主缓存中的命中块传送到接收缓存，使得数据可以存储在接收高速缓存中。 当指令处理器请求对接收缓存中保存的数据的访问时，数据被检索到指令处理器并且同时被传送到主缓存。

公开(公告)号：US06049221A

公开(公告)日：2000-04-11

申请号：US111804

申请日：1998-07-08

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Tsutomu Goto ,  Hideki Murayama ,  Akira Yamagiwa ,  Yasuhiro Ishii ,  Naoki Hamanaka ,  Masabumi Shibata

IPC分类号： H03K19/003 ,  H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/175

CPC分类号： H03K19/0005

摘要： A semiconductor integrated circuit system having a function of automatically adjusting an output resistance value with reference to a temperature of an LSI which is operating. When a count value obtained from a counter by counting the output of a timer becomes equal to a predetermined value, a temperature sensor measures temperatures of LSIs. If a temperature fluctuation measured from a previous measured value is greater than a predetermined width, then a control apparatus issues an output resistance value adjustment request signal to output resistance adjustment units of the LSIs. When receiving the output resistance value adjustment request signal, the output resistance value adjustment units stop the signal transmission between the LSIs, adjust output resistance values of output circuits in such a manner that the output resistance values are matched with a characteristic impedance of a transmission line, and maintains the adjusted output resistance values until the output resistance value adjustment units receive next output resistance value adjustment request signal.

摘要翻译： 具有参照正在运行的LSI的温度来自动调整输出电阻值的功能的半导体集成电路系统。 当通过对计时器的输出进行计数而得到的计数值等于预定值时，温度传感器测量LSI的温度。 如果从先前测量值测量的温度波动大于预定宽度，则控制装置发出输出电阻值调整请求信号以输出LSI的电阻调节单元。 当接收到输出电阻值调整请求信号时，输出电阻值调节单元停止LSI之间的信号传输，以输出电阻值与传输线的特性阻抗匹配的方式调整输出电路的输出电阻值 并保持调整后的输出电阻值直到输出电阻值调整单元接收到下一个输出电阻值调整请求信号。

公开(公告)号：US5867679A

公开(公告)日：1999-02-02

申请号：US647773

申请日：1991-01-30

申请人： Teruo Tanaka ,  Naoki Hamanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Junji Nakagoshi ,  Kazuo Ojima

发明人： Teruo Tanaka ,  Naoki Hamanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Junji Nakagoshi ,  Kazuo Ojima

IPC分类号： G06F9/44 ,  G06F15/17 ,  G06F15/80 ,  G06F15/82

CPC分类号： G06F15/8015 ,  G06F9/4494 ,  G06F15/17

摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.

摘要翻译： 并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。 数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。 提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

公开(公告)号：US5842207A

公开(公告)日：1998-11-24

申请号：US911617

申请日：1992-07-10

申请人： Shinji Fujiwara ,  Yooichi Shintani ,  Mitsuru Nagasaka ,  Naoki Hamanaka ,  Mikiko Suzuki

发明人： Shinji Fujiwara ,  Yooichi Shintani ,  Mitsuru Nagasaka ,  Naoki Hamanaka ,  Mikiko Suzuki

IPC分类号： G06F7/24 ,  G06F17/30

CPC分类号： G06F7/24 ,  Y10S707/99937

摘要： A sorting method used with a distributed database having a plurality of first processors for holding partial records of a database that is divided into a plurality of portions and a host processor for accessing to each of the first processors. The method comprises the steps of: assigning a plurality of sections into which the distribution range of key values of records of the database is partitioned to a plurality of second processors in the first processors, and information for representing storage positions of the records to the second processors to which the sections of the key values, to which the records belong, are assigned; and sorting the plurality of key values, which have been received, in the second processors to produce key tables in which the information for representing the storage positions of the records which has been received is registrated together with the sorted key values, as the sorting result.

摘要翻译： 一种与分布式数据库一起使用的排序方法，所述分布式数据库具有多个第一处理器，用于保存被划分成多个部分的数据库的部分记录以及用于访问每个第一处理器的主机处理器。 该方法包括以下步骤：将数据库的记录的键值的分配范围分配到多个第一处理器中的多个第二处理器的多个区段，以及用于将记录的存储位置表示到第二处理区域的信息 分配了记录所属键值的部分的处理器; 并且将已经接收到的多个密钥值排序在第二处理器中以产生密钥表，其中用于表示已经接收的记录的存储位置的信息与排序的关键字一起被登记在一起作为排序结果 。

公开(公告)号：US5386566A

公开(公告)日：1995-01-31

申请号：US853427

申请日：1992-03-18

申请人： Naoki Hamanaka ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Hiroyuki Chiba ,  Shin'ichi Shutoh ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

发明人： Naoki Hamanaka ,  Junji Nakagoshi ,  Tatsuo Higuchi ,  Hiroyuki Chiba ,  Shin'ichi Shutoh ,  Shigeo Takeuchi ,  Yasuhiro Ogata ,  Taturu Toba

IPC分类号： G06F9/46 ,  H04L29/00 ,  G06F13/00

CPC分类号： G06F9/544 ,  H04L29/00

摘要： In a parallel computer, in order to reduce the overhead of data transmissions between the processes, a data transmission from the virtual space of a process in a certain cluster to the virtual space of a process in other cluster is executed without copying the data to the buffer provided within the operating system. The real communication area resident in the real memory is provided in a part of the virtual space of the process, and an identifier unique within the cluster is given to the communication area. When the transmission process has issued a transmission instruction at the time of data transmission, the cluster address of the cluster in which the transmission destination process exists and the identifier of the communication area are determined based on the name of the transmission destination process. Then, the data is directly transmitted between the mutual real communication areas of the transmission originating process and the transmission destination process. Overhead for the data transmission between the processes can be reduced by avoiding making a copy of the data between the user space and the buffer provided within the operating system at the time of data transmission between the processes.

摘要翻译： 在并行计算机中，为了减少进程之间的数据传输的开销，执行从某个群集中的进程的虚拟空间到其他群集中的进程的虚拟空间的数据传输，而不将数据复制到 在操作系统中提供缓冲区。 驻留在真实存储器中的实际通信区域被提供在该进程的虚拟空间的一部分中，并且在群集内唯一的标识符被提供给通信区域。 当发送处理在数据发送时发出发送指示时，基于发送目的地处理的名称确定发送目的地处理所在的群集的群集地址和通信区域的标识符。 然后，数据在发送始发处理的相互实际通信区域和发送目的地处理之间直接发送。 可以通过在进程之间的数据传输时避免在用户空间和在操作系统内提供的缓冲区之间的数据的副本来复制用于进程之间的数据传输的开销。

公开(公告)号：US5086498A

公开(公告)日：1992-02-04

申请号：US145614

申请日：1988-01-10

申请人： Teruo Tanaka ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Teruo Tanaka ,  Naoki Hamanaka ,  Junji Nakagoshi ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F15/8092 ,  G06F15/17 ,  G06F15/173

摘要： In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.

摘要翻译： 在多处理器数字计算机系统ID数据中，与期望的处理器间通信的数据相耦合，从一个处理器传送并暂时保存在接收处理器中的接收缓冲器（关联存储器）中的数据。 该ID被划分为主ID数据MK和子ID数据SK。 主ID数据MK用于从接收缓冲器搜索数据。 子ID数据SK用作接收处理器中的数据的ID。