公开(公告)号：US06516391B1

公开(公告)日：2003-02-04

申请号：US09523737

申请日：2000-03-13

申请人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1200

CPC分类号： G06F12/0813 ,  G06F12/0817 ,  G06F15/177 ,  G06F2212/2542

摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

摘要翻译： 在根据其中包含多个处理器单元的多个处理器节点经由网络彼此耦合的NUMA或UMA而布置的多处理器中，结合存储器访问操作执行的高速缓存侦听操作在两个阶段 即在节点内执行的本地侦听操作，以及节点之间的全局侦听操作。 在执行本地侦听操作之前，向具有存储器的目标节点发出用于指定存储器的RAS的ACTV命令，并且预先激活存储器访问。 另外指定存储器的CAS，并且在发出ACTV命令之后重新执行存储器访问，然后发出存储器访问命令。 当存在待访问的存储器存在除了源节点之外的处理器节点的可能性时，该存储器访问命令被发布以分发给所有节点，以便执行全局侦听操作。 另一方面，当不存在要访问的存储器被缓存时，该存储器访问命令仅以一对一对应的方式传送到目标节点。

公开(公告)号：US06591325B1

公开(公告)日：2003-07-08

申请号：US09547392

申请日：2000-04-11

申请人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1314

CPC分类号： G06F13/4204

摘要： An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.

摘要翻译： 一种在多个系统模块之间传送交易的信息处理系统。 请求侧模块中的请求侧接口单元具有请求ID队列，其中发出的请求事务按照发布的顺序存储。 请求侧队列指针指向与要接受的响应事务相对应的该请求ID队列中的条目。 响应侧模块中的响应侧接口单元具有响应队列，其中接受请求事务按接受顺序存储。 响应侧队列指针指向对应于接下来要发出的响应事务的该响应队列中的条目。 因此，在请求侧接口单元和响应侧接口单元之间传送请求事务和相应的响应事务，而不转移事务ID。 当响应顺序改变时，响应侧接口单元发出改变请求侧队列指针的值的命令，以通知请求侧接口单元的顺序改变。

公开(公告)号：US06389518B1

公开(公告)日：2002-05-14

申请号：US09523737

申请日：2000-03-13

申请人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1200

摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

公开(公告)号：US06438653B1

公开(公告)日：2002-08-20

申请号：US09330981

申请日：1999-06-14

申请人： Hideya Akashi ,  Toshio Okochi ,  Toru Shonai ,  Masamori Kashiyama

发明人： Hideya Akashi ,  Toshio Okochi ,  Toru Shonai ,  Masamori Kashiyama

IPC分类号： G06F1206

CPC分类号： G06F12/0831 ,  G06F12/0864

摘要： A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing “summarized information” which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.

摘要翻译： 多处理器系统包括在各个处理器节点中的多个处理器节点控制电路和作为外部高速缓存的高速缓存存储器。 每个处理器节点控制电路包括总结高速缓存标签存储器，用于通过汇总高速缓冲存储器中的高速缓存标签部分上的信息并指示每个块是否被有效地索引到存储器中来存储具有减少位数的信息的“汇总信息” 缓存标签部分。 对于高速缓存一致性控制，首先访问汇总的高速缓存标签存储器，使得只有在确定目标块被有效地索引时才能访问高速缓存标签部分，以确定是否需要该节点的高速缓存一致性控制。

公开(公告)号：US5822329A

公开(公告)日：1998-10-13

申请号：US949783

申请日：1997-10-14

申请人： Kazunori Nakajima ,  Noboru Masuda ,  Tadaaki Isobe ,  Masamori Kashiyama ,  Bunichi Fujita ,  Masakazu Yamamoto

发明人： Kazunori Nakajima ,  Noboru Masuda ,  Tadaaki Isobe ,  Masamori Kashiyama ,  Bunichi Fujita ,  Masakazu Yamamoto

IPC分类号： G06F5/06 ,  G06K5/04 ,  G11B5/00

CPC分类号： G06F5/06

摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

摘要翻译： 在信息处理系统中的多个单元之间的发送和接收信号中，可以在由周期（频率）相同但不必相同的异步时钟操作的电路之间发送和接收信号，从而允许 信息处理系统在较短的时钟周期内运行。 布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。 此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。 延迟电路由决定结果自动控制。

公开(公告)号：US5001626A

公开(公告)日：1991-03-19

申请号：US512580

申请日：1990-04-20

申请人： Masamori Kashiyama ,  Hitoshi Abe

发明人： Masamori Kashiyama ,  Hitoshi Abe

IPC分类号： G06F17/16 ,  G06F15/78

CPC分类号： G06F15/8076

摘要： In a vector processor in which a plurality of load/store pipelines from a plurality of arithmetic units and a main storage are used for input/output operations of vector data on a plurality of vector registers in a parallel fashion, vector data is communicated between the respective modules constituting a physically closed system. A sequence of odd-numbered vector data elements and a sequence of even-numbered vector data elements each having a phase difference of a half of a period of a basic machine cycle are communicated at a speed of the basic machine cycle. The module includes vector registers, each vector register is constituted with two RAM arrays being independently addressable and being capable of performing read and write operations at a speed which is twice the basic machine cycle. The two vector data element sequences are converted into a vector data element sequence having a speed which is twice the machine cycle such that the respective vector data elements are alternately written and read in the RAM arrays at a speed which is twice the basic machine cycle. The vector data element sequence thus read out is converted into a sequence of odd-numbered vector data elements and even numbered vector data elements each having a speed of the basic machine cycle and thus the attained vector data element sequences are output.

摘要翻译： 在其中多个运算单元和主存储器的多个加载/存储管道以并行方式用于多个向量寄存器上的向量数据的输入/输出操作的向量处理器中，向量数据在 各个模块构成物理上封闭的系统。 以基本机器周期的速度来传送奇数矢量数据元素的序列和每个具有基本机器周期的周期的一半的相位差的偶数矢量数据元素的序列。 该模块包括向量寄存器，每个向量寄存器由两个可独立寻址的RAM阵列构成，能够以基本机器周期的两倍的速度执行读写操作。 两个向量数据元素序列被转换成具有两倍于机器周期的速度的向量数据元素序列，使得相应的矢量数据元素以基本机器周期的两倍的速度交替写入和读取到RAM阵列中。 这样读出的矢量数据元素序列被转换为奇数矢量数据元素和偶数矢量数据元素的序列，每个矢量数据元素具有基本机器周期的速度，从而输出所获得的矢量数据元素序列。

公开(公告)号：US20120161692A1

公开(公告)日：2012-06-28

申请号：US13333390

申请日：2011-12-21

申请人： Yuichi Kobayashi ,  Keisuke Shirai ,  Masamori Kashiyama ,  Shimon Morii

发明人： Yuichi Kobayashi ,  Keisuke Shirai ,  Masamori Kashiyama ,  Shimon Morii

IPC分类号： H02J7/00 ,  H01M10/46

CPC分类号： B60L58/13 ,  Y02T10/7005 ,  Y02T10/7044 ,  Y02T10/705

摘要： In a charging control system, electrically-driven vehicles whose charging levels are lower than such a charging level required to drive these electrically-driven vehicles over a necessary minimum drivable distance are charged with a priority, and such an electrically-driven vehicle whose charging level quickly reaches the above-explained charging level among these electrically-driven vehicles is charged with a top priority. Also, in the charging control system, an order for dynamically charging vehicle-purpose batteries is rearranged by monitoring a change in charging environments, for instance, an electrically-driven vehicle is newly coupled to a charger in a half way; a commonly available electric power amount is increased by solar power generation etc.; and a supplyable electric power amount (W) is lowered due to utilization of electricity by a subject other than electrically-driven vehicles.

摘要翻译： 在充电控制系统中，充电水平低于在必要的最小可驱动距离上驱动这些电动车辆所需的充电水平的电动车辆被优先充电，并且这种电动车辆的充电水平 在这些电动车辆中快速达到上述充电水平被最高优先地收费。 此外，在充电控制系统中，通过监视充电环境的变化来重新布置用于动态充电车用电池的顺序，例如，电动车辆以一半方式新连接到充电器; 通过太阳能发电等增加通常的电力量; 并且可供电电力量（W）由于电动车辆以外的物体的电力而被降低。

公开(公告)号：US20090209282A1

公开(公告)日：2009-08-20

申请号：US12388073

申请日：2009-02-18

申请人： Yuichi Kobayashi ,  Masamori Kashiyama

发明人： Yuichi Kobayashi ,  Masamori Kashiyama

IPC分类号： H04M1/00 ,  H04W4/02

CPC分类号： H04W28/18 ,  H04W48/18 ,  H04W64/006

摘要： According to one aspect of wireless communication control apparatus and method for a mobile object according to the present invention, the wireless communication apparatus and method include the steps of: collecting communication-state information corresponding to positional information of the mobile object for each of a plurality of communication methods that are used to make a connection to a wireless communication device of the mobile object, and that can be selectively set in the wireless communication device; referring to the communication-state information corresponding to the positional information indicating a current position of the mobile object, and selecting one communication method from among the plurality of communication methods that can be selectively set in the wireless communication device; and setting, in the wireless communication device, control information used for communications based on the selected communication method.

摘要翻译： 根据本发明的移动体的无线通信控制装置和方法的一个方面，所述无线通信装置和方法包括以下步骤：收集与多个移动体对应的移动体的位置信息相对应的通信状态信息 用于与移动对象的无线通信设备建立连接并且可以在无线通信设备中选择性地设置的通信方法; 参照与表示移动体的当前位置的位置信息对应的通信状态信息，从无线通信装置中可以选择设定的多个通信方式中选择一种通信方式; 以及在所述无线通信设备中，基于所选择的通信方法来设置用于通信的控制信息。

公开(公告)号：US5729550A

公开(公告)日：1998-03-17

申请号：US618787

申请日：1996-03-20

申请人： Kazunori Nakajima ,  Noboru Masuda ,  Tadaaki Isobe ,  Masamori Kashiyama ,  Bunichi Fujita ,  Masakazu Yamamoto

发明人： Kazunori Nakajima ,  Noboru Masuda ,  Tadaaki Isobe ,  Masamori Kashiyama ,  Bunichi Fujita ,  Masakazu Yamamoto

IPC分类号： G06F5/06 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20

CPC分类号： G06F5/06

摘要： In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

摘要翻译： 在信息处理系统中的多个单元之间发送和接收信号时，可以在由周期（频率）相同但不一定相位的异步时钟操作的电路之间发送和接收信号，从而允许 信息处理系统在较短的时钟周期内运行。 布置在通信路径中的延迟电路是可控的，使得与发送单元的时钟信号同步发送的数据与接收单元的时钟信号同步正确检索。 此外，与发送单元的时钟信号同步地发送具有预定简单模式的数据，并且确定数据是否已被接收单元正确地接收。 延迟电路由决定结果自动控制。

公开(公告)号：US08768624B2

公开(公告)日：2014-07-01

申请号：US13322234

申请日：2010-05-26

申请人： Yuichi Kobayashi ,  Yuzuru Fukuda ,  Masamori Kashiyama

发明人： Yuichi Kobayashi ,  Yuzuru Fukuda ,  Masamori Kashiyama

IPC分类号： G01C21/34 ,  B60W20/00 ,  G05D1/02 ,  G01C21/26

CPC分类号： B60W20/00 ,  B60L3/12 ,  B60L11/184 ,  B60L11/1846 ,  B60L2230/16 ,  B60L2240/12 ,  B60L2240/622 ,  B60L2240/72 ,  B60L2240/80 ,  B60L2250/16 ,  B60L2260/52 ,  B60L2260/54 ,  B60L2260/58 ,  B60L2270/32 ,  B60W20/11 ,  G01C21/26 ,  G01C21/34 ,  G01C21/3469 ,  G05D1/0278 ,  G08G1/096816 ,  G08G1/09685 ,  Y02T10/7005 ,  Y02T10/7088 ,  Y02T10/7291 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/16 ,  Y02T90/161 ,  Y02T90/162 ,  Y02T90/163 ,  Y02T90/169 ,  Y04S30/14

摘要： A vehicle drive support system, and its method, includes a storage apparatus for storing charging station information to manage attribute information containing position information of charging stations, a communication apparatus for receiving a route search request containing an origin, a destination, and a residual quantity in a battery from a mobile and transmitting a response to the route search request, and a route search processing unit for searching a route passing through the charging stations while maintaining a state in which the residual quantity in the battery is greater than 0 between the origin and the destination by using position information of the charging stations contained in the charging station information in response to the route search request received by the communication apparatus, and giving the searched route as the response to the route search request.

摘要翻译： 车辆驱动支持系统及其方法包括：存储装置，用于存储充电站信息以管理包含充电站的位置信息的属性信息;通信装置，用于接收包含原点，目的地和剩余量的路线搜索请求 在来自移动台的电池中并且发送对路线搜索请求的响应;以及路线搜索处理单元，用于搜索通过充电站的路线，同时保持电池中的剩余量在原点之间大于0的状态 以及响应于由通信装置接收到的路由搜索请求，通过使用包含在充电站信息中的充电站的位置信息，并将搜索到的路线作为对路线搜索请求的响应来进行目的地。