公开(公告)号：US20130021092A1

公开(公告)日：2013-01-24

申请号：US13009868

申请日：2011-01-20

申请人： Prasun Kali BHATTACHARYYA ,  Sumanth Chakkirala ,  Prakash Easwaran

发明人： Prasun Kali BHATTACHARYYA ,  Sumanth Chakkirala ,  Prakash Easwaran

IPC分类号： H03K5/00

CPC分类号： H03H7/0153 ,  H03H7/06 ,  H03H11/12 ,  H03H2210/012 ,  H03H2210/028

摘要： An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

摘要翻译： 超低截止频率滤波器。 滤波电路包括响应于输入信号和反馈信号的控制电路以产生控制信号。 滤波器电路包括耦合到控制电路的可控电阻器。 可控电阻响应于参考信号和控制信号以产生反馈信号。 滤波器电路包括耦合到控制电路和可控电阻器的反馈路径，以将来自可控电阻器的反馈信号耦合到控制电路，从而从输入信号和参考信号中的至少一个消除噪声，并且防止电压误差 在滤波电路中。

公开(公告)号：US20100164606A1

公开(公告)日：2010-07-01

申请号：US12463390

申请日：2009-05-09

申请人： Prakash EASWARAN ,  Prasenjit BHOWMIK ,  Sumeet MATHUR

发明人： Prakash EASWARAN ,  Prasenjit BHOWMIK ,  Sumeet MATHUR

IPC分类号： G05F1/10

CPC分类号： G05F3/26 ,  H03F1/301

摘要： A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

摘要翻译： 用于偏置MOS晶体管的方法包括将来自放大器级的输入信号AC耦合到MOS晶体管的栅极。 该方法包括将一对相反并联配置的二极管连接到偏置晶体管和电流源。 此外，该方法包括通过偏置晶体管和电流源产生DC偏置电压。 该方法还包括通过钳位电路将偏置晶体管的漏极处的电压钳位到固定电压。 此外，该方法包括通过一对二极管将DC偏置电压耦合到MOS晶体管的栅极。

公开(公告)号：US20090295609A1

公开(公告)日：2009-12-03

申请号：US11760743

申请日：2007-06-09

申请人： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

发明人： T. S. Venkatesh ,  L. Chandrashekar ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  C. Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/0641 ,  H03M1/12

摘要： A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

摘要翻译： 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。

公开(公告)号：US06480068B1

公开(公告)日：2002-11-12

申请号：US09966055

申请日：2001-09-28

申请人： Fernando A. Mujica ,  Prakash Easwaran ,  Sandeep Kesrimal Oswal

发明人： Fernando A. Mujica ,  Prakash Easwaran ,  Sandeep Kesrimal Oswal

IPC分类号： H03G310

CPC分类号： H03G3/3042

摘要： The present invention provides a hardware assisted automatic gain control (AGC) for a communication network. A dedicated hardware portion of the AGC, which works in cooperation with software implemented functionality (400), is included to detect saturation conditions in the internal nodes of the analog front end (200) in which a plurality of gain stages (PGA1, PGA2, PGA3) and filter stages (H1, H2, H3) are interleaved with inaccessible intermediate points. The saturation detection logic includes a comparator (21, 22, 23) and flip-flop (27, 28, 29) for each gain stage (PGA1, PGA2, PGA3) and can be integrated directly in the analog front end 200. The dedicated hardware can further be included in a codec of a modem in a digital subscriber line (DSL) system.

摘要翻译： 本发明提供了一种用于通信网络的硬件辅助自动增益控制（AGC）。 包括与软件实现的功能（400）协同工作的AGC的专用硬件部分，以检测模拟前端（200）的内部节点中的饱和状态，其中多个增益级（PGA1，PGA2， PGA3）和滤波器级（H1，H2，H3）与不可访问的中间点交错。 饱和检测逻辑包括用于每个增益级（PGA1，PGA2，PGA3）的比较器（21,22,23）和触发器（27,28,29），并且可以直接集成在模拟前端200中。专用 硬件可以进一步包括在数字用户线（DSL）系统中的调制解调器的编解码器中。