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10 条记录 (耗时 0.031 秒)

    Leakage independent very low bandwith current filter
    5.
    发明授权
    Leakage independent very low bandwith current filter 有权
    漏电独立非常低带电滤波器

    公开(公告)号：US07868688B2

    公开(公告)日：2011-01-11

    申请号：US12463389

    申请日：2009-05-09

    申请人： Prakash Easwaran ,  Prasenjit Bhowmik ,  Sumeet Mathur

    发明人： Prakash Easwaran ,  Prasenjit Bhowmik ,  Sumeet Mathur

    IPC分类号： H03K5/00

    CPC分类号： H03F3/345

    摘要： A current filter circuit is provided. The current filter circuit comprises a source transistor comprising a drain, a gate, and a source. The source of the source transistor is coupled to a reference voltage terminal, the gate of the source transistor is coupled to the gate of a mirror transistor, and the drain of the source transistor is coupled to a reference current source. The mirror transistor comprises a drain, a gate, and a source. The source of the mirror transistor is coupled to the reference voltage terminal, the gate is coupled to the gate of the source transistor, and the drain is coupled to a load. The current filter circuit comprises a low pass filter for filtering noise. The current filter circuit also comprises an impedance reduction circuit coupled to the drain of the mirror transistor for reducing bandwidth of the current filter circuit.

    摘要翻译： 提供电流滤波电路。 电流滤波器电路包括源极晶体管，源极晶体管包括漏极，栅极和源极。 源极晶体管的源极耦合到参考电压端子，源极晶体管的栅极耦合到反射镜晶体管的栅极，源极晶体管的漏极耦合到参考电流源。 反射镜晶体管包括漏极，栅极和源极。 反射镜晶体管的源极耦合到参考电压端子，栅极耦合到源极晶体管的栅极，并且漏极耦合到负载。 电流滤波电路包括用于滤除噪声的低通滤波器。 电流滤波器电路还包括耦合到镜晶体管的漏极的阻抗减小电路，用于减小电流滤波器电路的带宽。

    DC biasing circuit for a metal oxide semiconductor transistor
    6.
    发明授权
    DC biasing circuit for a metal oxide semiconductor transistor 有权
    用于金属氧化物半导体晶体管的直流偏置电路

    公开(公告)号：US08106706B2

    公开(公告)日：2012-01-31

    申请号：US12463390

    申请日：2009-05-09

    申请人： Prakash Easwaran ,  Prasenjit Bhowmik ,  Sumeet Mathur

    发明人： Prakash Easwaran ,  Prasenjit Bhowmik ,  Sumeet Mathur

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： G05F3/26 ,  H03F1/301

    摘要： A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

    摘要翻译： 用于偏置MOS晶体管的方法包括将来自放大器级的输入信号AC耦合到MOS晶体管的栅极。 该方法包括将一对相反并联配置的二极管连接到偏置晶体管和电流源。 此外，该方法包括通过偏置晶体管和电流源产生DC偏置电压。 该方法还包括通过钳位电路将偏置晶体管的漏极处的电压钳位到固定电压。 此外，该方法包括通过一对二极管将DC偏置电压耦合到MOS晶体管的栅极。

    Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof
    7.
    发明授权
    Multi-phase delay locked loop with equally-spaced phases over a wide frequency range and method thereof 有权
    在宽频率范围内具有等间隔相位的多相延迟锁相环及其方法

    公开(公告)号：US07675333B2

    公开(公告)日：2010-03-09

    申请号：US11760782

    申请日：2007-06-10

    申请人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  Sriram Ganesan

    发明人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  Sriram Ganesan

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

    摘要翻译： 公开了一种用于在宽频率范围内产生多个等间隔相位的延迟锁定环（DLL）和方法。 DLL包括延迟线和控制模块。 延迟线接收参考时钟信号，并响应于参考时钟信号输出最终延迟时钟信号。 延迟线包括串联连接的多个延迟单元。 多个延迟单元产生具有相等间隔相位的多个延迟时钟信号。 控制模块基于在最终延迟时钟信号的第一对应脉冲发生之前对输入到延迟线的参考时钟信号的脉冲数进行计数来产生相位控制信号。

    Delay line with delay cells having improved gain and in built duty cycle control and method thereof
    8.
    发明授权
    Delay line with delay cells having improved gain and in built duty cycle control and method thereof 失效
    具有改善增益的延迟单元和内置占空比控制的延迟线及其方法

    公开(公告)号：US07548104B2

    公开(公告)日：2009-06-16

    申请号：US11760784

    申请日：2007-06-10

    申请人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

    发明人： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

    IPC分类号： H03H11/26

    CPC分类号： H03K5/1565 ,  H03H11/265 ,  H03K5/133 ,  H03K2005/00045

    摘要： A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

    摘要翻译： 公开了一种包括具有改善的增益和内置的占空比失真控制的相同延迟单元序列的延迟线及其方法。 序列的每个延迟单元包括电流源，四个晶体管和负载电容器。 电流源的栅极接收控制延迟单元的延迟的电压偏置。 第一晶体管的漏极连接到电流源的漏极。 第一和第二晶体管栅极接收输入时钟信号。 第二晶体管漏极连接到电流源的源极。 第三晶体管栅极和负载电容器也连接到电流源的漏极。 第四晶体管漏极连接到第三晶体管漏极。 第四晶体管栅极耦合到用于占空比失真控制的第二连续延迟单元的输出。

    Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation
    9.
    发明授权
    Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation 有权
    松弛振荡器电路具有降低的振荡频率灵敏度对比较器的延迟变化

    公开(公告)号：US08659362B2

    公开(公告)日：2014-02-25

    申请号：US13301806

    申请日：2011-11-22

    申请人： Prasenjit Bhowmik ,  Rishi Mathur ,  Sriram Ganesan ,  Sunil Rajan

    发明人： Prasenjit Bhowmik ,  Rishi Mathur ,  Sriram Ganesan ,  Sunil Rajan

    IPC分类号： H03K3/00

    CPC分类号： H03K4/502 ,  H03K3/0231

    摘要： A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

    摘要翻译： 具有降低的振荡频率对比较器延迟变化的灵敏度的张弛振荡器电路包括产生充电电流的第一电流源，耦合到第一电流源以产生参考电压的第二电流源，耦合到第二电流源的电阻器，以产生 参考电压耦合到基于充电电流而被充电的电容器，响应于与电容器相对应的电压的比较器和参考电压以产生输出电压;峰值检测器，耦合到电容器以产生峰值 电压，耦合到所述峰值检测器和所述第二电流源的误差检测器，以基于所述峰值电压和所述参考电压产生误差;以及控制器，耦合到所述误差检测器以控制输入到所述电压的所述充电电流， 比较器和电容器的电容。

    RELAXATION OSCILLATOR CIRCUIT WITH REDUCED SENSITIVITY OF OSCILLATION FREQUENCY TO COMPARATOR DELAY VARIATION
    10.
    发明申请
    RELAXATION OSCILLATOR CIRCUIT WITH REDUCED SENSITIVITY OF OSCILLATION FREQUENCY TO COMPARATOR DELAY VARIATION 有权
    具有降低振荡灵敏度的放大振荡器电路与比较器延迟变化

    公开(公告)号：US20120319789A1

    公开(公告)日：2012-12-20

    申请号：US13301806

    申请日：2011-11-22

    申请人： Prasenjit Bhowmik ,  Rishi Mathur ,  Sriram Ganesan ,  Sunil Rajan

    发明人： Prasenjit Bhowmik ,  Rishi Mathur ,  Sriram Ganesan ,  Sunil Rajan

    IPC分类号： H03K3/02

    CPC分类号： H03K4/502 ,  H03K3/0231

    摘要： A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

    摘要翻译： 具有降低的振荡频率对比较器延迟变化的灵敏度的张弛振荡器电路包括产生充电电流的第一电流源，耦合到第一电流源以产生参考电压的第二电流源，耦合到第二电流源的电阻器，以产生 参考电压耦合到基于充电电流而被充电的电容器，响应于与电容器相对应的电压的比较器和参考电压以产生输出电压;峰值检测器，耦合到电容器以产生峰值 电压，耦合到所述峰值检测器和所述第二电流源的误差检测器，以基于所述峰值电压和所述参考电压产生误差;以及控制器，耦合到所述误差检测器以控制输入到所述电压的所述充电电流， 比较器和电容器的电容。