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公开(公告)号：US20070285297A1
公开(公告)日：2007-12-13
申请号：US11760746
申请日：2007-06-09
申请人： T. S. Venkatesh , L. Chandrashekar , Prasun Kali Bhattacharya , Prasenjit Bhowmik , C. Srinivasan , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
发明人： T. S. Venkatesh , L. Chandrashekar , Prasun Kali Bhattacharya , Prasenjit Bhowmik , C. Srinivasan , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
IPC分类号： H03M1/12
CPC分类号： H03M1/0641 , H03M1/12
摘要： A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.
摘要翻译： 一种通过随机化差分失配来改善模数转换器（ADC）中的动态性能的系统和方法。 通过随机翻转输入信号和输出信号，输入模拟信号的差分失配被随机化。
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2.发明申请SYSTEM AND METHOD FOR REDUCING POWER DISSIPATION IN AN ANALOG TO DIGITAL CONVERTER 有权用于减少模拟数字转换器中的功率消耗的系统和方法公开(公告)号：US20090295609A1
公开(公告)日：2009-12-03
申请号：US11760743
申请日：2007-06-09
申请人： T. S. Venkatesh , L. Chandrashekar , Prasun Kali Bhattacharya , Prasenjit Bhowmik , C. Srinivasan , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
发明人： T. S. Venkatesh , L. Chandrashekar , Prasun Kali Bhattacharya , Prasenjit Bhowmik , C. Srinivasan , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
CPC分类号： H03M1/0641 , H03M1/12
摘要： A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.
摘要翻译： 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。
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公开(公告)号：US07538701B2
公开(公告)日：2009-05-26
申请号：US11760746
申请日：2007-06-09
申请人： Venkatesh Teeka Srinivasa Shetty , Chandrashekar Lakshminarayanan , Prasun Kali Bhattacharya , Prasenjit Bhowmik , Srinivasan Chakravarthy , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
发明人： Venkatesh Teeka Srinivasa Shetty , Chandrashekar Lakshminarayanan , Prasun Kali Bhattacharya , Prasenjit Bhowmik , Srinivasan Chakravarthy , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
IPC分类号： H03M1/20
CPC分类号： H03M1/0641 , H03M1/12
摘要： A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.
摘要翻译： 一种通过随机化差分失配来改善模数转换器（ADC）中的动态性能的系统和方法。 通过随机翻转输入信号和输出信号，输入模拟信号的差分失配被随机化。
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4.发明授权System and method for reducing power dissipation in an analog to digital converter 有权用于降低模数转换器功耗的系统和方法公开(公告)号：US07821436B2
公开(公告)日：2010-10-26
申请号：US11760743
申请日：2007-06-09
申请人： Venkatesh Teeka Srinvasa Setty , Chandrashekar Lakshminarayanan , Prasun Kali Bhattacharya , Prasenjit Bhowmik , Chakravarthy Srinivasan , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
发明人： Venkatesh Teeka Srinvasa Setty , Chandrashekar Lakshminarayanan , Prasun Kali Bhattacharya , Prasenjit Bhowmik , Chakravarthy Srinivasan , Mukesh Khatri , Sanjeeb Kumar Ghosh , Sumanth Chakkirala , Sundararajan Krishnan , Prakash Easwaran
IPC分类号： H03M3/00
CPC分类号： H03M1/0641 , H03M1/12
摘要： A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.
摘要翻译： 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。
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公开(公告)号：US08912843B2
公开(公告)日：2014-12-16
申请号：US13009868
申请日：2011-01-20
CPC分类号： H03H7/0153 , H03H7/06 , H03H11/12 , H03H2210/012 , H03H2210/028
摘要： An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.
摘要翻译： 超低截止频率滤波器。 滤波电路包括响应于输入信号和反馈信号的控制电路以产生控制信号。 滤波器电路包括耦合到控制电路的可控电阻器。 可控电阻响应于参考信号和控制信号以产生反馈信号。 滤波器电路包括耦合到控制电路和可控电阻器的反馈路径，以将来自可控电阻器的反馈信号耦合到控制电路，从而从输入信号和参考信号中的至少一个消除噪声，并且防止电压误差 在滤波电路中。
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公开(公告)号：US20130021092A1
公开(公告)日：2013-01-24
申请号：US13009868
申请日：2011-01-20
IPC分类号： H03K5/00
CPC分类号： H03H7/0153 , H03H7/06 , H03H11/12 , H03H2210/012 , H03H2210/028
摘要： An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.
摘要翻译： 超低截止频率滤波器。 滤波电路包括响应于输入信号和反馈信号的控制电路以产生控制信号。 滤波器电路包括耦合到控制电路的可控电阻器。 可控电阻响应于参考信号和控制信号以产生反馈信号。 滤波器电路包括耦合到控制电路和可控电阻器的反馈路径，以将来自可控电阻器的反馈信号耦合到控制电路，从而从输入信号和参考信号中的至少一个消除噪声，并且防止电压误差 在滤波电路中。
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7.发明申请CIRCUIT FOR OPTIMIZING A POWER MANAGEMENT SYSTEM DURING VARYING LOAD CONDITIONS 有权在变化的负载条件下优化电源管理系统的电路公开(公告)号：US20130021094A1
公开(公告)日：2013-01-24
申请号：US13009869
申请日：2011-01-20
CPC分类号： H03F1/0277 , H03F2200/393
摘要： A circuit for optimizing a power management system. The circuit includes a first amplifier. The first amplifier is responsive to a first reference signal and operable to supply a first load current. The circuit also includes a second amplifier coupled to the first amplifier. The second amplifier is responsive to a second reference signal and operable to supply a second load current. The second load current is lower in magnitude than the first load current, thereby enabling the first amplifier to operate during a first load condition, and the second amplifier to operate during the first load condition and a second load condition. Further, the circuit includes a resistive element coupled to the first amplifier and the second amplifier, to isolate the first amplifier from the second amplifier.
摘要翻译： 用于优化电源管理系统的电路。 电路包括第一放大器。 第一放大器响应于第一参考信号并且可操作以提供第一负载电流。 电路还包括耦合到第一放大器的第二放大器。 第二放大器响应于第二参考信号并且可操作以提供第二负载电流。 第二负载电流的幅度比第一负载电流低，从而使得第一放大器能够在第一负载状态下工作，并且第二放大器在第一负载状态和第二负载状态期间工作。 此外，电路包括耦合到第一放大器和第二放大器的电阻元件，以将第一放大器与第二放大器隔离。
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8.发明授权Circuit for optimizing a power management system during varying load conditions 有权用于在变化的负载条件下优化电源管理系统的电路公开(公告)号：US08736363B2
公开(公告)日：2014-05-27
申请号：US13009869
申请日：2011-01-20
CPC分类号： H03F1/0277 , H03F2200/393
摘要： A circuit for optimizing a power management system. The circuit includes a first amplifier. The first amplifier is responsive to a first reference signal and operable to supply a first load current. The circuit also includes a second amplifier coupled to the first amplifier. The second amplifier is responsive to a second reference signal and operable to supply a second load current. The second load current is lower in magnitude than the first load current, thereby enabling the first amplifier to operate during a first load condition, and the second amplifier to operate during the first load condition and a second load condition. Further, the circuit includes a resistive element coupled to the first amplifier and the second amplifier, to isolate the first amplifier from the second amplifier.
摘要翻译： 用于优化电源管理系统的电路。 电路包括第一放大器。 第一放大器响应于第一参考信号并且可操作以提供第一负载电流。 电路还包括耦合到第一放大器的第二放大器。 第二放大器响应于第二参考信号并且可操作以提供第二负载电流。 第二负载电流的幅度比第一负载电流低，从而使得第一放大器能够在第一负载状态下工作，并且第二放大器在第一负载条件和第二负载条件期间操作。 此外，电路包括耦合到第一放大器和第二放大器的电阻元件，以将第一放大器与第二放大器隔离。
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